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PDF HSP43881JC-30 Data sheet ( Hoja de datos )
| Número de pieza | HSP43881JC-30 | |
| Descripción | Digital Filter | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HSP43881
May 1999 File Number 2758.4
Digital Filter
The HSP43881 is a video speed Digital Filter (DF) designed
to efficiently implement vector operations such as FIR digital
filters. It is comprised of eight filter cells cascaded internally
and a shift and add output stage, all in a single integrated
circuit. Each filter cell contains a 8 x 8-bit multiplier, three
decimation registers and a 26-bit accumulator. The output
stage contains an additional 26-bit accumulator which can
add the contents of any filter cell accumulator to the output
stage accumulator shifted right by 8 bits. The HSP43881 has
a maximum sample rate of 30MHz. The effective multiply
accumulate (mac) rate is 240MHz.
The HSP43881 DF can be configured to process expanded
coefficient and word sizes. Multiple DFs can be cascaded for
larger filter lengths without degrading the sample rate or a
single DF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or two’s complement
arithmetic, independently selectable for coefficients and
signal data.
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of 1/2, 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and N x N spatial
correlations/convolutions for image processing applications.
Features
• Eight Filter Cells
• 0MHz to 30MHz Sample Rate
• 8-Bit Coefficients and Signal Data
• 26-Bit Accumulator Per Stage
• Filter Lengths Over 1000 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
• Sample Rate Converters
Ordering Information
PART
NUMBER
HSP43881JC-20
HSP43881JC-25
TEMP. RANGE
(oC)
PACKAGE
0 to 70
84 Ld PLCC
0 to 70
84 Ld PLCC
PKG. NO.
N84.1.15
N84.1.15
HSP43881JC-30
HSP43881GC-20
HSP43881GC-25
0 to 70
0 to 70
0 to 70
84 Ld PLCC
85 Ld PGA
85 Ld PGA
N84.1.15
G85.A
G85.A
HSP43881GC-30
0 to 70
85 Ld PGA G85.A
Block Diagram
VCC VSS
DIN0 - DIN7 TCS
DIENB
CIENB
DCMO - 1
ERASE
5
8
TCCI
CIN0 - 7 8
DF
FILTER 8
CELL 0
RESET 5
CLK
ADR0 - 2
5
3
26
8
8
DF
FILTER 8
CELL 1
26
8
DF
FILTER 8
CELL 2
26
8
DF
FILTER 8
CELL 3
26
MUX
RESET
CLK
SHADD
SENBL
SENBH
ADR0, ADR1, ADR2
2
2
26
OUTPUT
STAGE
26
SUM0 - 25
8
DF
FILTER 8
CELL 4
26
8
DF
FILTER 8
CELL 5
26
8
DF
FILTER 8
CELL 6
26
8
DF
FILTER 8
CELL 7
26
TCCO
COUT0 - 7
COENB
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HSP43881
Pin Description (Continued)
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
DCM0-1
G2, L1
These two inputs determine the use of the internal decimation registers as follows:
DCM1 DCM0
Decimation Function
0 0 Decimation Registers not used.
0 1 One Decimation Register is used.
1 0 Two Decimation Registers are used.
1 1 Three Decimation Registers are used.
The coefficients pass from cell to cell at a rate determined by the number of decimation registers
used. When no decimation registers are used, coefficients move from cell to cell on each clock.
When one decimation register is used, coefficients move from cell to cell on every other clock, etc.
These signals are latched and delayed by one clock internal to the DF.
SUM0-25
J2, J5-8, J10,
K2, K5-11,
L-26, L8,
L10-11
O These 26 three-state outputs are used to output the results of the internal filter cell computations.
Individual filter cell results or the result of the shift and add output stage can be output. If an individ-
ual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal
determines whether the selected filter cell result or the output stage adder result is output. The sig-
nals SENBH and SENBL enable the most significant and least significant bits of the SUM0-25 result,
respectively. Both SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or
larger bus. However, individual enables are provided to facilitate use with a 16-bit bus.
SENBH K1 I A low on this input enables result bits SUM16-25. A high on this input places these bits in their high
impedance state.
SENBL E11 I A low on this input enables result bits SUM0-15. A high on this input places these bits in their high
impedance state.
ADR0-2
G1, H1-2
I These inputs select the one cell whose accumulator will be read through the output bus (SUM0-25)
or added to the output stage accumulator. They also determine which accumulator will be cleared
when ERASE is low. For selection of which accumulator to read through the output bus (SUM0-25)
or which to add to the output stage accumulator, these inputs are latched in the DF and delayed by
one clock internal to the device. If the ADR0-2 lines remain at the same address for more than one
clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first clock, when ADR0-1 selects the cell, will be
output. This does not hinder normal operation since the ADR0-1 lines are changed sequentially.
This feature facilitates the interface with slow memories where the output is required to be fixed for
more than one clock.
SHADD F3 I The SHADD input controls the activation of the shift-and-add operation in the output stage. This
signal is latched in the DF and delayed by one clock internal to the device. A detailed explanation is
given in the DF Output Stage Section.
RESET A4 I A low on this input synchronously clears all the internal registers, except the cell accumulators. It
can be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in
the DF and delayed by one clock internal to the DF.
ERASE B4 I A low on this input synchronously clears the cell accumulator selected by the ADR0-1 signals. If
RESET is also low simultaneously, all cell accumulators are cleared.
ALIGN PIN
C3
Used for aligning chip in socket or printed circuit board. Must be left as a no connect in circuit.
Functional Description
The Digital Filter Processor (DF) is composed of eight filter cells
cascaded together and an output stage for combining or
selecting filte5r cell outputs (See Block Diagram). Each filter cell
contains a multiplier accumulator and several registers (Figure
1). Each 8-bit coefficient is multiplied by an 8-bit data sample,
with the result added to the 26-bit accumulator contents. The
coefficient output of each cell is cascaded to the coefficient
input of the next cell to its right.
DF Filter Cell
An 8-bit coefficient (CIN0-7) enters each cell through the C
register on the left and exits the cell on the right as signals
COUT0-7. With no decimation, the coefficient moves directly
from the C register to the output, and is valid on the clock
following its entrance. When decimation is selected the
coefficient exit is delayed by 1, 2 or 3 clocks by passing through
one or more decimation registers (D1, D2 or D3).
The combination of D registers through which the coefficient
passes is determined by the state of DCM0 and DCM1. The
output signals (COUT0-7) are connected to the CIN0-7 inputs
of the next cell to its right. The COENB input signal enables the
COUT0-7 outputs of the right most cell to the COUT-07 pins of
the device.
The C and D registers are enabled for loading by CIENB.
Loading is synchronous with CLK when CIENB is low. Note that
5
5 Page 
HSP43881
CLK
RESET
ERASE
DIN0-7
DIENB
CIN0-7
CIENB
ADR0-2
SUM0-24
SHADD
SENBL
SENBH
DCM0-1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18
C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5 C4 C3 C2 C1 C0 C7 C6 C5
012345670
Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14
0
7
∑YN =
CK × XN – K
K=0
FIGURE 4. 30MHz, 8-TAP FIR FILTER TIMING
11
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