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PDF HSP43891GC-20 Data sheet ( Hoja de datos )
| Número de pieza | HSP43891GC-20 | |
| Descripción | Digital Filter | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HSP43891
May 1999 File Number 2785.5
Digital Filter
The HSP43891 is a video-speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells
cascaded internally and a shift and add output stage, all in
a single integrated circuit. Each filter cell contains a 9x9
two’s complement multiplier, three decimation registers and
a 26-bit accumulator. The output stage contains an
additional 26-bit accumulator which can add the contents of
any filter cell accumulator to the output stage accumulator
shifted right by 8-bits. The HSP43891 has a maximum
sample rate of 30MHz. The effective multiply-accumulate
(mac) rate is 240MHz.
The HSP43891 DF can be configured to process expanded
coefficient and word sizes. Multiple DFs can be cascaded
for larger filter lengths without degrading the sample rate or
a single DF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter
coefficients are less than 1.0, making even larger filter
lengths possible. The DF provides for 8-bit unsigned or
9-bit two’s complement arithmetic, independently
selectable for coefficients and signal data.
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of 1/2, 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and NxN spatial
correlations/convolutions for image processing applications.
Features
• Eight Filter Cells
• 0MHz to 30MHz Sample Rate
• 9-Bit Coefficients and Signal Data
• 26-Bit Accumulator per Stage
• Filter Lengths Over 1000 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Digital Video
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
- Sample Rate Converters
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG. NO.
HSP43891VC-20
0 to 70 100 Lead MQFP Q100.14x20
HSP43891VC-25
0 to 70 100 Lead MQFP Q100.14x20
HSP43891VC-30
0 to 70 100 Lead MQFP Q100.14x20
HSP43891JC-20
0 to 70
84 Lead PLCC N84.1.15
HSP43891JC-25
0 to 70
84 Lead PLCC N84.1.15
HSP43891JC-30
0 to 70
84 Lead PLCC N84.1.15
HSP43891GC-20
0 to 70
85 Pin CPGA G85.A
HSP43891GC-25
0 to 70
85 Pin CPGA G85.A
HSP43891GC-30
0 to 70
85 Pin CPGA G85.A
Block Diagram
VCC VSS
DIENB
CIENB
DCM0 - 1
ERASE
5
9
CIN0 - 8
DF
FILTER 9
CELL 0
DIN0 - DIN8
9
DF
FILTER 9
CELL 1
DF
FILTER 9
CELL 2
DF
FILTER 9
CELL 3
RESET 5 5
26
26
26
26
CLK
ADRO - 2
3
MUX
RESET
CLK
SHADD
SENBL
SENBH
ADR0, ADR1, ADR2
2
2
26
OUTPUT
STAGE
26
SUM0 - 25
DF
FILTER 9
CELL 4
26
DF
FILTER 9
CELL 5
26
DF
FILTER 9
CELL 6
26
DF
FILTER 9
CELL 7
26
COUT0 - 8
COENB
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HSP43891
Pin Description (Continued)
SYMBOL
PIN
NUMBER
TYPE
NAME AND FUNCTION
SUM0-25
F9, G9-G11,
H10, H11, J2,
J5-J7, J10, K2,
K5, K7-K11,
L2-L6, L8, L10,
L11
O These 26 three-state outputs are used to output the results of the internal filter cell computations. Indi-
vidual filter cell results or the result of the shift and add output stage can be output. If an individual filter
cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal determines
whether the selected filter cell result or the output stage adder result is output. The signals SENBH and
SENBL enable the most significant and least significant bits of the SUM0-25 result respectively. Both
SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or larger bus. However
individual enables are provided to facilitate use with a 16-bit bus.
SENBH
K1
I A low on this input enables result bits SUM16-25. A high on this input places these bits in their high
impedance state.
SENBL
E11
I A low on this input enables result bits SUM0-15. A high on this input places these bits in their high im-
pedance state.
ADR0-2
G1, H1, H2
I These three inputs select the one cell whose accumulator will be read through the output bus (SUM0-
25) or added to the output stage accumulator. They also determine which accumulator will be cleared
when ERASE is low. These inputs are latched in the DF and delayed by one clock internal to the device.
If ADR0-2 remains at the same address for more than one clock, the output at SUM0-25 will not change
to reflect any subsequent accumulator updates in the addressed cell. Only the result available during
the first clock, when ADR0-2 selects the cell, will be output. This does not hinder normal operation since
the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories
where the output is required to be fixed for more than one clock.
SHADD
F3
I The SHADD input controls the activation of the shift and add operation in the output stage. This signal
is latched on chip and delayed by one clock internal to the device. Detailed explanation is given in the
DF Output Stage section.
RESET
A4
I A low on this input synchronously clears all the internal registers, except the cell accumulators It can
be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in the DF
and delayed by one clock internal to the device.
ERASE
B4
I A low on this input synchronously clears the cell accumulator selected by the ADR0-2 signals. If RESET
is also low simultaneously, all cell accumulators are cleared.
Functional Description
The Digital Filter Processor (DF) is composed of eight filter
cells cascaded together and an output stage for combining
or selecting filter cell outputs (See Block Diagram). Each
filter cell contains a multiplier-accumulator and several
registers (Figure 1). Each 9-bit coefficient is multiplied by a
9-bit data sample, with the result added to the 26-bit
accumulator contents. The coefficient output of each cell is
cascaded to the coefficient input of the next cell to its right.
DF Filter Cell
A 9-bit coefficient (CIN0-8) enters each cell through the C
register on the left and exits the cell on the right as signals
COUT0-8. With no decimation, the coefficient moves directly
from the C register to the output, and is valid on the clock
following its entrance. When decimation is selected the
coefficient exit is delayed by 1, 2 or 3 clocks by passing
through one or more decimation registers (D1, D2 or D3).
The combination of D registers through which the coefficient
passes is determined by the state of DCM0 and DCM1. The
output signals (COUT0-8) are connected to the CIN0-8
inputs of the next cell to its right. The COENB input signal
enables the COUT0-8 outputs of the right most cell to the
COUT0-8 pins of the device.
The C and D registers are enabled for loading by CIENB.
Loading is synchronous with CLK when CIENB is low. Note
that CIENB is latched internally. It enables the register for
loading after the next CLK following the onset of CIENB low.
Actual loading occurs on the second CLK following the onset
of CIENB low. Therefore CIENB must be low during the clock
cycle immediately preceding presentation of the coefficient
on the CIN0-8 inputs. In most basic FIR operations, CIENB
will be low throughout the process, so this latching and delay
sequence is only important during the initialization phase.
When CIENB is high, the coefficients are frozen.
The C and D registers are cleared synchronously under control
of RESET, which is latched and delayed exactly like CIENB.
The output of the C register (C0-8) is one input to 9 x 9
multiplier.
The other input to the 9 x 9 multiplier comes from the output
of the X register. This register is loaded with a data sample
from the device input signals DIN0-8 discussed above. The
X register is enabled for loading by DIENB. Loading is
synchronous with CLK when DIENB is low. Note that DIENB
is latched internally. It enables the register for loading after
the next CLK following the onset of DIENB low. Actual
loading occurs on the second CLK following the onset of
DIENB low; therefore, DIENB must be low during the clock
5
5 Page 
HSP43891
Extended FIR Filter Length Filter
lengths greater that eight taps can be created by either
cascading together multiple DF devices or “reusing” a single
device. Using multiple devices, an FIR filter of over 1000
taps can be constructed to operate at a 30MHz sample rate.
Using a single device clocked at 30MHz, an FIR filter of over
500 taps can be constructed to operate at less than a
30MHz sample rate. Combinations of these two techniques
are also possible.
Cascade Configuration
To design a filter length L>8, L/8 DFs are cascaded by
connecting the COUT0-8 outputs of the (i)th DF to the CIN0-
8 inputs of the (i+1)th DF. The DIN0-8fs inputs and SUM0-25
outputs of all the DFs are also tied together. A specific
example of two cascaded DFs illustrates the technique
(Figure 5). Timing (Figure 6) is similar to the simple 8-tap
FIR, except the ERASE and SENBL/SENBH signals must be
enabled independently for the two DFs in order to clear the
correct accumulators and enable the SUM0-25 output
signals at the proper times.
TABLE 2.
DATA SEQUENCE INPUT X30 . . . X9, X8, X22 . . . X1, X0
COEFFICIENT SEQUENCE INPUT C0 . . . C14, C15, 0 . . . C0 . . . C14, C15
HSP43891
. . . 0, Y30 . . . Y23, 0. . . 0, Y22 . . . Y15, 0. . . 0
CLK
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CELL 0
C15 x X0
+C14 x X1
+C13 x X2
+C12 x X3
+C11 x X4
+C10 x X5
+C9 x X6
+C8 x X7
+C7 x X8
+C6 x X9
+C5 x X10
+C4 x X11
+C3 x X12
+C2 x X13
+C1 x X14
+C0 x X15
0
0
0
0
0
0
0
C15 x X8
+C14 x X9
+C13 x X10
+C12 x X11
+C11 x X12
+C10 x X13
+C9 x X14
+C8 x X15
+C7 x X16
+C6 x X17
+C5 x X18
+C4 x X19
+C3 x X20
+C2 x X21
+C1 x X22
+C0 x X23
0
0
0
0
CELL 1
0
C15 x X1
C0 x X16
0
0
0
0
0
0
0
+C15 x X9
C0 x X23
0
0
0
CELL 2
0
0
C15 x X2
C0 x X17
0
0
0
0
0
0
0
+C15 x X10
C0 x X25
0
0
CELL 3
0
0
0
C15 x X3
+C14 x X4
+C13 x X5
+C12 x X6
+C11 x X7
+C10 x X8
+C9 x X9
+C8 x X10
+C7 x X11
+C6 x X12
+C5 x X13
+C4 x X14
+C3 x X15
+C2 x X16
+C1 x X17
+C0 x X18
0
0
0
0
0
0
0
+C15 x X11
C0 x X26
0
CELL 4
-
-
-
-
C15 x X4
C0 x X19
0
0
0
0
0
0
0
+C15 x X12
C0 x X27
CELL 5
-
-
-
-
-
C15 x X5
C0 x X20
0
0
0
0
0
0
0
+C15 x X12
CELL 6
-
-
-
-
-
-
C15 x X6
C0 x X21
0
0
0
0
0
0
0
+C15 x X14
CELL 7
-
-
-
-
-
-
-
C15 x X7
+C14 x X8
+C13 x X9
+C12 x X10
+C11 x X11
+C10 x X12
+C9 x X13
+C8 x X14
+C7 x X15
+C6 x X16
+C5 x X17
+C4 x X18
+C3 x X19
+C2 x X20
+C1 x X21
+C0 x X22
0
0
0
0
0
0
0
C15 x X15
+C14 x X16
+C13 x X17
+C12 x X18
+C11 x X19
+C10 x X20
+C9 x X21
+C8 x X22
+C7 x X23
+C6 x X24
+C5 x X25
+C4 x X26
+C3 x X27
SUM/CLR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Cell 0 (Y15)
Cell 1 (Y16)
Cell 2 (Y17)
Cell 3 (Y18)
Cell 4 (Y19)
Cell 5 (Y20)
Cell 6 (Y21)
Cell 7 (Y22)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Cell 0 (Y23)
Cell 1 (Y24)
Cell 2 (Y25)
Cell 3 (Y26)
Cell 4 (Y27)
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet HSP43891GC-20.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HSP43891GC-20 | Digital Filter | Intersil Corporation |
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