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PDF Am29LV320B Data sheet ( Hoja de datos )
| Número de pieza | Am29LV320B | |
| Descripción | 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit 3.0 Volt-only Boot Sector Flash Memory | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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DATASHEET
Am29LV320MT/B
32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit
3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■ Single power supply operation
— 3 V for read, erase, and program operations
■ Manufactured on 0.23 µm MirrorBit process
technology
■ SecSi (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
■ Flexible sector architecture
— Sixty-three 32 Kword/64-Kbyte sectors
— Eight 4 Kword/8 Kbyte boot sectors
■ Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
■ Minimum 100,000 erase cycle guarantee per sector
■ 20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■ High performance
— 90 ns access time
— 25 ns page read times
— 0.5 s typical sector erase time
— 15 µs typical effective write buffer word programming
time: 16-word/32-byte write buffer reduces overall
programming time for multiple-word/byte updates
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer
■ Low power consumption (typical values at 3.0 V, 5
MHz)
— 13 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
■ Package options
— 48-pin TSOP
— 48-ball Fine-pitch BGA
— 64-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
■ Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■ Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
— WP#/ACC input:
Write Protect input (WP#) protects top or bottom two
sectors regardless of sector protection settings
ACC (high voltage) accelerates programming time for
higher throughput during system production
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 26518 Rev: B Amendment/0
Issue Date: May 16, 2003
Refer to AMD’s Website (www.amd.com) for the latest information.
1 page  
DATASHEET
PRODUCT SELECTOR GUIDE
Part Number
Speed
Option
VCC = 3.0–3.6 V
VCC = 2.7–3.6 V
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page access time (tPACC)
Max. OE# Access Time (ns)
90R
90
90
25
25
100R
100
100
100
30
30
Am29LV320MT/B
110R
110
110
110
30 40
30 40
120R
120
120
30
30
120
40
40
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
RY/BY#
VCC
VSS
RESET#
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
CE#
OE#
Sector Switches
Erase Voltage
Generator
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
DQ0–DQ15 (A-1)
Input/Output
Buffers
STB
Data
Latch
VCC Detector
A20–A0
Timer
STB
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
May 16, 2003
Am29LV320MT/B
5
5 Page 
DATASHEET
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing spec-
ifications and to Figure 14 for the timing diagram.
Refer to the DC Characteristics table for the active
current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad-
dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an
asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Fast page mode ac-
cesses are obtained by keeping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 3 and 2 indicates the
address space that each sector occupies.
Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Char-
acteristics section contains timing specification tables
and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system to write a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. See
“Write Buffer” for more information.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that the WP#/ACC pin must not
be at VHH for operations other than accelerated pro-
gramming, or device damage may result. In addition,
no external pullup is necessary since the WP#/ACC
pin has internal pullup to VCC.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode,
but the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
May 16, 2003
Am29LV320MT/B
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Am29LV320B.PDF ] | |
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