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PDF CXB1452Q Data sheet ( Hoja de datos )
| Número de pieza | CXB1452Q | |
| Descripción | VGA/SVGA/XGA digital data serial receiver | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXB1452Q
VGA/SVGA/XGA digital data serial receiver
Features
• 1 chip receiver for serial transmission of 18bit color
VGA/SVGA/XGA picture
• On chip differential cable driver
• TTL/CMOS compatible interface
• Support 1 pixel/shiftclock mode & 2 pixel/shiftclock
mode
• +3.3V single power supply
• Low power consumption
• 80pin Plastic QFP Package
(Body size: 14mm × 14mm)
Block Digagram & Pin out
80 pin QFP (Plastic)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
TESTDT 61
PANEL1 62
PANEL0 63
CKMODE 64
CNTL3 65
CNTL2 66
CNTL1 67
VEEG 68
VCCG 69
VCCT 70
VEET 71
SFTCLK 72
HSYNC 73
VSYNC 74
VEEG 75
VCCG 76
CNTL0 77
BLU1 (5) 78
BLU1 (4) 79
VCCT 80
CDR
PLL
Cable
EQ
Serial
to
Parallell
Converter
Decoder
40 VCCT
39 GRN0 (0)
38 GRN0 (1)
37 GRN0 (2)
36 GRN0 (3)
35 GRN0 (4)
34 GRN0 (5)
33 VEEG
32 VCCG
31 VEET
30 VCCT
29 BLU0 (0)
28 BLU0 (1)
27 BLU0 (2)
26 VEEG
25 VCCG
24 BLU0 (3)
23 BLU0 (4)
22 BLU0 (5)
21 VEET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Fig. 1. Block Diagram & Pin out
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97937-PS
1 page  
CXB1452Q
VCCA/G/T
AA
61 51
VCC CXB1452Q
55 54
VEEA/G/T
Fig. 2. IOH_RQ and IOL_RQ DC measurement
Tab. 4. AC Characteristics (Under the recommended conditons. See Tab. 5)
Description
SFTCLK frequency
SFTCLK duty factor
Symbol
Fsftclk
Dsftclk
Min.
20.0
10.0
38.0
19.0
60.0
30.0
35
Pixel/Sync/Cntl setup to
SFTCLK
Tsetup
24.0
11.0
3.5
20.0
Pixel/Sync/Cntl hold to
SFTCLK
Thold
SFTCLK rise time
SFTCLK fall time
Pixel/Sync/Cntl rise time
Pixel/Sync/Cntl fall time
CLOCK mode assert time
CLOCK mode deassert time
LOS signal assert time
LOS signal deassert time
Torc
Tofc
Tord
Tord
TAclk
TDclk
TAlos
TDlos
6.5
4.0
2.5
1.0
Typ.
25.0
12.5
40.0
20.0
65.0
32.5
0.9
50
0.8
0.1
Max.
28.0
14.0
48.0
24.0
68.0
34.0
65
4.0
3.0
7.0
6.0
Unit Conditions
MHz
MHz
MHz
MHz
MHz
MHz
VGA, 1 pixel/sftclk mode
VGA, 2 pixel/sftclk mode
SVGA, 1 pixel/sftclk mode
SVGA, 2 pixel/sftclk mode
XGA, 1 pixel/sftclk mode
XGA, 2 pixel/sftclk mode
% Vth = 1.4V, CL = 10pF
Vth = 1.4V, CL = 10pF
ns VGA, 1 pixel/sftclk 25MHz
ns SVGA, 1 pixel/sftclk 40MHz
ns XGA, 1 pixel/sftclk 65MHz
ns XGA, 2 pixel/sftclk 32.5MHz
Vth = 1.4V, CL = 10pF
ns VGA, 1 pixel/sftclk 25MHz
ns SVGA, 1 pixel/sftclk 40MHz
ns XGA, 1 pixel/sftclk 65MHz
ns XGA, 2 pixel/sftclk 32.5MHz
ns 0.8V to 2.0V, CL = 10pF
ns 2.0V to 0.8V, CL = 10pF
ns 0.8V to 2.0V, CL = 10pF
ns 2.0V to 0.8V, CL = 10pF
µs
µs
µs
µs
–5–
5 Page 
Recommended Printed Circuit Board Structure
L1: Cu plate (18µm) + solder coat
I1: Adhesive Sheet (0.3mm ± 0.09mm)
L2: Cu plate (36µm)
I2: Fiber-glass epoxy core (0.8mm)
L3: Cu plate (36µm)
I3: Adhesive Sheet (0.3mm)
L4: Cu plate (18µm) + solder coat
Recommended Printed Circuit Board Pattern
SDATAP/SDATAN pins to the connector path
other path
W = 0.50mm (Z0 = 50Ω)
W = 0.25mm
POWER and special signal routing example
0.5mm
CXB1452Q
L2 doesn't have plane
in this area
60
To LOS
61
G
E
80
TESTDT
PANEL1
PANEL0
CKMODE
CNTL3
CNTL2
CNTL1
VEEG
VCCG
VCCT
VEET
SFTCLK
HSYNC
VSYNC
VEEG
VCCG
CNTL0
BLU1 (5)
BLU1 (4)
VCCT
E
G
G
1
G
TT T T
TT T T
G
– 11 –
G Through hole to the GND plane (L2)
E Through hole to the VCCE/VCCG plane (L3)
T Through hole to the VCCT plane (L3)
Chip capacitor
Chip resistor
FET
41
G
VCCT
40
GRN0 (0)
GRN0 (1)
GRN0 (2)
GRN0 (3)
GRN0 (4)
GRN0 (5)
VEEG
E VCCG
G
VEET
VCCT
BLU0 (0)
BLU0 (1)
BLU0 (2)
G VEEG
VCCG
BLU0 (3)
E
BLU0 (4)
BLU0 (5)
VEET
21
G
20
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CXB1452Q.PDF ] | |
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