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PDF CXD2436Q Data sheet ( Hoja de datos )
| Número de pieza | CXD2436Q | |
| Descripción | Timing Generator for LCD Panels | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD2436Q
Timing Generator for LCD Panels
For the availability of this product, please contact the sales office.
Description
The CXD2436Q is a timing signal generator for the
100 pin QFP (Plastic)
VGA LCD panel LCX012 driver. This chip has a
built-in serial interface circuit which allows the mode
to be switched with respect to various VGA signals
through direct control from an external
microcomputer, etc.
Features
• Generates the LCX012 drive pulse.
• Supports three-panel projectors.
• Built-in serial interface circuit
• Supports various VGA signals. (non-interlaced
mode)
• Built-in 2-line pair drive circuits
• Supports NTSC and PAL systems.
• Supports up/down and/or right/left inversion.
• Supports line inversion and field inversion.
• Generates timing signal of external sample-and-
hold circuit.
Applications
LCD projectors, etc.
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VDD VSS–0.5 to +7.0 V
• Input voltage
VI VSS–0.5 to VDD+0.5 V
• Output voltage
VO VSS–0.5 to VDD+0.5 V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage
VDD +4.5 to +5.5
• Supply voltage
VCC –20 to +75
V
°C
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E95810-TE
1 page  
CXD2436Q
Pin
Symbol
No.
83 XRGT
84 HST
85 HCK1
86 HCK2
87 CLR
88 ENB
89 INT
90 VSS
91 PCG
92 VCK
93 VST1
94 SH1
95 SH2
96 SH3
97 SH4
98 SH5
99 SH6
100 SH7
I/O Description
O Right/left inversion discrimination signal output
O H start pulse output (positive polarity)
O H clock pulse 1 output
O H clock pulse 2 output
O CLR pin output
O ENB pin output
O INT pin output
O GND
O PCG pin output (positive polarity)
O V clock pulse output
O V start pulse output
O Sample-and-hold pulse 1 (positive polarity)
O Sample-and-hold pulse 2 (positive polarity)
O Sample-and-hold pulse 3 (positive polarity)
O Sample-and-hold pulse 4 (positive polarity)
O Sample-and-hold pulse 5 (positive polarity)
O Sample-and-hold pulse 6 (positive polarity)
O Sample-and-hold pulse 7 (positive polarity)
Input pin for
open status
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Electrical Characteristics
1. DC characteristics
Item Symbol
Conditions
(Temperature = 25 °C, VSS = 0 V)
Min. Typ. Max. Unit Applicable pins
Supply voltage
Input voltage 1
Input voltage 2
VDD
VIH1
VIL1
CMOS input cell
VIH2
CMOS Schmitt
VIL2
trigger input cell
VT+ –VT+
4.5 5.0 5.5 V
0.7 VDD
Input pins other than
V
0.3 VDD
those noted below
0.8 VDD
HDnIN, VDnIN, CSYNC,
0.2 VDD V CKI, PWM, TC, PEO,
0.6 CKO, SI, SCK, CS
VOH
Output voltage 1
VOL
IOH=–2 mA
IOL=4 mA
VDD–0.8
Output pins other than
V
0.4 those noted below
VOH
Output voltage 2
VOL
IOH=–4 mA
IOL=8 mA
VDD–0.8
V VCK
0.4
VOH
Output voltage 3
VOL
VOH
Output voltage 4
VOL
Input leak
IIL
current
IIH
IOH=–6 mA
VDD–0.8
IOL=12 mA
IOH=–3 mA
VDD/2
IOL=3 mA
Pull-up resistor connected –40
Pull-down resistor connected 40
–100
100
0.4
VDD/2
–240
240
V HCKn, SHn, HST
V CKO, PEO
∗1
µA
SI
Output leak
current
Current
consumption
ILZ
IDD
High impedance
status
fclk=31 MHz
VDD=5.0 V
–40 40 µA RPD, FPD
55 mA At no load
∗1 Input pins with pull-up resistors
HPOL, VPOL, XCLR, PLNT, VGAV, SLDWN, SLRGT, SLFR, TST1, SLSY, TST2, TST3, SLCKI, TST9, SCK, CS
—5—
5 Page 
CXD2436Q
• XCLR (External clear)
Reset should be performed during startup in order to initialize the serial interface. Performing external
clear sets all serial interface modes to Low.
• Serial interface specifications
The CXD2436Q can set and switch the driving mode with the serial interface.
Set the corresponding timing data for each VGA signal according to the format in the diagram below. Be
sure to make the initial mode settings. (See the AC characteristics for detailed timing specifications.)
CS
SCK
SI D0 D1 D2 D3 D4 D5 D6 D7
Fig. 1. Timing chart for the serial interface input block
Note) D0 to D7 internal transfer is completed by the CS signal switching from a Low to High pulse. Therefore,
the data should be transferred in 1-byte units with the CS signal reset each time.
• Description of mode switching settings using the serial interface
The CXD2436Q can set the following six modes.
(1) Frequency division ratio setting for the 1/N frequency divider of the master clock PLL circuit block.
(2) H screen center adjustment. The center changes by one dot with LSB.
(3) V screen center adjustment. The center changes by one line with LSB.
(4) Sample-and-hold circuit phase adjustment. The phase changes by a half-dot with LSB.
(See the Description of Sample-and-Hold Timing for details.)
(5) Clamp pulse timing adjustment (4-way)
(6) Data output (Serial data is held and output.)
Upper 4-bit
address value
Lower 4-bit data
Functions
D7 to D4
D3
D2
D1
D0
0H PHP3 PHP2 PHP1 PHP0
PLL 1/N frequency
1H PHP7 PHP6 PHP5 PHP4
divisions
2H — PHP10 PHP9 PHP8
3H HP3 HP2 HP1 HP0 H screen center
4H — HP6 HP5 HP4 adjustment
5H VP3 VP2 VP1 VP0 V screen center
6H — VP6 VP5 VP4 adjustment
7H SHP3 SHP2 SHP1 SHP0 S/H timing
8H — — CLPP1 CLPP0 Clamp timing
9H
PO3
PO2
PO1
PO0
AH
PO7
PO6
PO5
PO4 Data output
BH
PO11 PO10 PO9
PO8
∗ PHP0, HP0, VP0, SHP0, CLPP0
—11—
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD2436Q.PDF ] | |
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