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PDF CXD3003 Data sheet ( Hoja de datos )
| Número de pieza | CXD3003 | |
| Descripción | CD Digital Signal Processor with Built-in Digital Servo and DAC | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD3003R
CD Digital Signal Processor with Built-in Digital Servo and DAC
For the availability of this product, please contact the sales office.
Description
The CXD3003R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter and 1-bit DAC.
144 pin LQFP (Plastic)
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular
Velocity)
• Frame jitter free
• 0.5× to 24× continuous playback possible with a
low external clock
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1× to 24× playback by switching the built-
in VCO
• The bit clock, which strobes the EFM signal, is
generated by the digital PLL
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error
correction
C1: double correction, C2: quadruple correction
Supported during 24× playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo (built-in oversampling filter)
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high
accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo
control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment function
• Surf jump function supporting micro two-axis
Digital Filter and DAC Blocks
• Digital de-emphasis
• Digital attenuation
• 4Fs oversampling filter
• Adoption of a secondary ∆∑ noise shaper
• Supports double-speed playback
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD
–0.3 to +4.6 V
• Input voltage
VI
–0.3 to +4.6 V
(VSS – 0.3V to VDD + 0.3V)
• Output voltage VO
–0.3 to +4.6 V
• Storage temperature Tstg
–40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Recommended Operating Conditions
• Supply voltage VDD∗
3.0 to 4.0
V
• Operating temperature
Topr
–20 to +75 °C
∗ The VDD (min.) for the CXD3003R varies
according to the playback speed and built-in VCO
selection. The VDD (min.) for the CXD3003R under
various conditions are as shown on the following
page.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97306A88
1 page  
CXD3003R
Pin Description
Pin Symbol
No.
I/O
Description
3 SE
I
Sled error signal input.
4 FE
I
Focus error signal input.
5 VC
I
Center voltage input.
6 VPCO1 O 1, Z, 0 Wide-band EFM PLL VCO2 charge pump output.
7
VPCO2
O
1, Z, 0
Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $E
command FCSW.
8 VCTL
I
Wide-band EFM PLL VCO2 control voltage input.
9 FILO
O Analog Master PLL filter output (slave = digital PLL).
10 FILI
I
Master PLL filter input.
11 PCO
O 1, Z, 0 Master PLL charge pump output.
12 CLTV
I
Multiplier VCO control voltage input.
13 AVSS1
Analog GND.
14 RFAC I
EFM signal input.
15 BIAS
I
Asymmetry circuit constant current input.
16 ASYI
I
Asymmetry comparator voltage input.
17 ASYO O 1, 0 EFM full-swing output (low = VSS, high = VDD).
18 AVDD1
Analog power supply.
20 DVDD1
Digital power supply.
21 DVSS1
Digital GND.
22 ASYE I
Asymmetry circuit on/off (low = off, high = on).
23 PSSL
I
Audio data output mode switching input (low: serial, high: parallel).
24 WDCK O 1, 0 D/A interface for 48-bit slot. Word clock f = 2Fs.
25 LRCK O 1, 0 D/A interface for 48-bit slot. LR clock f = Fs.
26 LRCKI I
LR clock input to DAC (48-bit slot).
27 DA16
O
1, 0
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
28 PCMDI I
Audio data input to DAC (48-bit slot).
29 DA15 O 1, 0 DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
30 BCKI
I
Bit clock input to DAC (48-bit slot).
31 DA14
O
1, 0
DA14 output when PSSL = 1, 64-bit slot serial data output (two's
complement, LSB first) when PSSL = 0.
32 DA13 O 1, 0 DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0.
33 DA12 O 1, 0 DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0.
34 DA11 O 1, 0 DA11 output when PSSL = 1, GTOP output when PSSL = 0.
39 DA10 O 1, 0 DA10 output when PSSL = 1, XUGF output when PSSL = 0.
40 DA09 O 1, 0 DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
–5–
5 Page 
(2) CLOK, DATA, XLAT, SQCK and EXCK pins
(VDD = AVDD = 3.3V ±10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK SQCK frequency
EXCK SQCK pulse width
CNIN frequency∗
CNIN pulse width∗
fCK
tWCK
tSU
tH
tD
tWL
fT
tWT
fT
tWT
30
30
30
30
750
750
7.5
16 MHz
ns
ns
ns
ns
ns
0.65 MHz
ns
65 kHz
µs
∗ Only when $44 and $45 are executed.
CLOK
1/fCK
tWCK
tWCK
DATA
XLAT
tSU tH
tD tWL
EXCK
SQCK
CNIN
tWT tWT
1/fT
SBSO
SQSO
tSU tH
CXD3003R
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD3003.PDF ] | |
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