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PDF DS75 Data sheet ( Hoja de datos )

Número de pieza DS75
Descripción Digital Thermometer and Thermostat
Fabricantes Dallas Semiconducotr 
Logotipo Dallas Semiconducotr Logotipo



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www.maxim-ic.com
FEATURES
ƒ Temperature Measurements Require No
External Components
ƒ Measures Temperatures from -55°C to
+125°C (-67°F to +257°F)
ƒ ±2°C Accuracy Over a -25°C to +100°C
Range
ƒ Thermometer Resolution is User-
Configurable from Nine (Default) to 12 Bits
(0.5°C to 0.0625°C Resolution)
ƒ 9-Bit Conversion Time is 150ms (Max)
ƒ Thermostatic Settings are User-Definable
ƒ Data is Read/Written Via 2-Wire Serial
(Interface (SDA and SCL Pins)
ƒ Multidrop Capability Simplifies Distributed
Temperature-Sensing Applications
ƒ Wide Power-Supply Range (+2.7V to
+5.5V).
ƒ Pin/software Compatible with the LM75
ƒ Available in 8-Pin μMAX® and SO
Packages. See Table 1 for Ordering
Information
ƒ Applications Include Personal Computers,
Cellular Base Stations, Office Equipment, or
Any Thermally Sensitive System
DS75
Digital Thermometer and Thermostat
PIN ASSIGNMENT
SDA 1
8 VDD
SCL 2
7 A0
O.S. 3
6 A1
GND 4
5 A2
DS75S+ (8-Pin SO — 150mil)
SDA
SCL
O.S.
GND
1
2
3
4
8 VDD
7 A0
6 A1
5 A2
DS75U+ (μMAX)
PIN DESCRIPTION
SDA – Open-Drain Data I/O
SCL – Clock Input
GND – Ground
O.S. – Open-Drain Thermostat Output
A0 – Address Input
A1 – Address Input
A2 – Address Input
V DD – Power Supply
DESCRIPTION
The DS75 digital thermometer and thermostat provides 9, 10, 11, or 12-bit digital temperature readings
over a -55°C to +125°C range with ±2°C accuracy over a -25°C to +100°C range. At power-up, the
DS75 defaults to 9-bit resolution for software compatibility with the LM75. Communication with the
DS75 is achieved via a simple 2–wire serial interface. Three address pins allow up to eight DS75 devices
to operate on the same 2–wire bus, which greatly simplifies distributed temperature sensing applications.
The DS75 thermostat has a dedicated open–drain output (O.S.) and programmable fault tolerance, which
allows the user to define the number of consecutive error conditions that must occur before O.S is
activated. There are two thermostatic operating modes that control thermostat operation based on user-
defined trip-points (TOS and THYST).
A block diagram of the DS75 is shown in Figure 1 and detailed pin descriptions are given in Table 2.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
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DS75 pdf
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL CONDITION
Resolution
Temperature
Conversion Time
tCONVT
9-bit
conversions
10-bit
conversions
11-bit
conversions
12-bit
conversions
SCL Frequency
Bus Free Time
Between a STOP and
START Condition
fSCL
tBUF
START and Repeated
START Hold Time
from Falling SCL
tHD:STA
Low Period of SCL
High Period of SCL
Repeated START
Condition Setup Time
to Rising SCL
tLOW
tHIGH
tSU:STA
Data-Out Hold Time
from Falling SCL
tHD:DAT
Data-In Setup Time to tSU:DAT
Rising SCL
Rise Time of SDA and
SCL
tR
Fall Time of SDA and
SCL
tF
STOP Setup Time to tSU:STO
Rising SCL
Capacitive Load for
Each Bus Line
CB
Input Capacitance
CI
DS75
(-55°C to +125°C; 2.7V VDD 5.5V)
MIN TYP MAX UNITS NOTES
9 12 bits
150 ms
300
600
1200
400 KHz
1.3 μs 5
0.6 μs 5, 6
1.3 μs 5
0.6 μs 5
0.6 μs 5
0
100
20 + 0.1CB
20 + 0.1CB
0.6
5
0.9
1000
300
400
μs
ns
ns
ns
μs
pF
pF
5
5
5, 7
5, 7
5
NOTES:
1. All voltages are referenced to ground.
2. Internal heating caused by O.S. loading will cause the DS75 to read approximately 0.5°C higher if
O.S. is sinking the max rated current.
3. IDD specified with O.S. pin open.
4. IDD specified with VDD at 5.0V and SDA, SCL = 5.0V, 0°C to 70°C.
5. See Timing Diagram in Figure 2. All timing is referenced to 0.9 x VDD and 0.1 x VDD.
6. After this period, the first clock pulse is generated.
7. For example, if CB = 300pF, then tR[min] = tF[min] = 50ns.
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DS75 arduino
DS75
START Condition: Signal generated by the master to indicate the beginning of a data transfer on the
bus. The master generates a START condition by pulling SDA from high to low while SCL is high (see
Figure 6). A “repeated” START is sometimes used at the end of a data transfer (instead of a STOP) to
indicate that the master will perform another operation.
STOP Condition: Signal generated by the master to indicate the end of a data transfer on the bus. The
master generates a STOP condition by transitioning SDA from low to high while SCL is high (see Figure
6). After the STOP is issued, the master releases the bus to its idle state.
Acknowledge (ACK): When a device (either master or slave) is acting as a receiver, it must generate an
acknowledge (ACK) on the SDA line after receiving every byte of data. The receiving device performs an
ACK by pulling the SDA line low for an entire SCL period (see Figure 6). During the ACK clock cycle,
the transmitting device must release SDA. A variation on the ACK signal is the “not acknowledge”
(NACK). When the master device is acting as a receiver, it uses a NACK instead of an ACK after the last
data byte to indicate that it is finished receiving data. The master indicates a NACK by leaving the SDA
line high during the ACK clock cycle.
Slave Address: Every slave device on the bus has a unique 7-bit address that allows the master to access
that device. The DS75’s 7-bit bus address is 1 0 0 1 A2 A1 A0, where A2, A1 and A0 are user-selectable via
the corresponding input pins. The three address pins allow up to eight DS75s to be multi-dropped on the
same bus.
Address Byte: The control byte is transmitted by the master and consists of the 7-bit slave address plus a
read/write (R/¯W¯) bit (see Figure 7). If the master is going to read data from the slave device then R/¯W¯ =
1, and if the master is going to write data to the slave device then R/¯W¯ = 0.
Pointer Byte: The pointer byte is used by the master to tell the DS75 which register is going to be
accessed during communication. The six LSbs of the pointer byte (see Figure 8) are always 0 and the two
LSbs correspond to the desired register as shown in Table 7.
Figure 6. START, STOP, AND ACK SIGNALS
SDA
SCL
START
Condition
ACK (or NACK) STOP
From Receiver Condition
Figure 7. ADDRESS BYTE
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1 0 0 1 A2 A1 A0 R/¯W¯
Figure 8. POINTER BYTE
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
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