PDF K4S281632B-N Data sheet ( Hoja de datos )

Número de pieza	K4S281632B-N
Descripción	2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP
Fabricantes	Samsung semiconductor
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No Preview Available ! K4S281632B-N shrink-TSOP 2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP CMOS SDRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) GENERAL DESCRIPTION The K4S281632B-N is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programma- ble burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications. ORDERING INFORMATION Part No. K4S281632B-NC/L1H K4S281632B-NC/L1L Max Freq. Interface Package 100MHz(CL=2) 100MHz(CL=3) LVTTL 54pin sTSOP(II) FUNCTIONAL BLOCK DIAGRAM Data Input Register CLK ADD Bank Select 2M x 16 2M x 16 2M x 16 2M x 16 Column Decoder LCKE LRAS LCBR LWE LCAS Latency & Burst Length Programming Register LWCBR Timing Register LWE LDQM DQi LDQM CLK CKE CS RAS CAS WE LDQM UDQM * Samsung Electronics reserves the right to change products or specification without notice. 1 page K4S281632B-N shrink-TSOP AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 3.3V Output 870Ω 1200Ω 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output CMOS SDRAM Unit V V ns V Z0 = 50Ω Vtt = 1.4V 50Ω 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version -1H -1L Unit Row active to row active delay tRRD(min) 20 ns RAS to CAS delay tRCD(min) 20 ns Row precharge time tRP(min) 20 ns Row active time tRAS(min) tRAS(max) 50 100 ns us Row cycle time tRC(min) 70 ns Last data in to row precharge tRDL(min) 2 CLK Last data in to Active delay tDAL(min) 2 CLK + 20 ns - Last data in to new col. address delay tCDL(min) 1 CLK Last data in to burst stop tBDL(min) 1 CLK Col. address to col. address delay tCCD(min) 1 CLK Number of valid output data CAS latency=3 CAS latency=2 2 ea 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. tRDL=1CLK and tDAL=1CLK+20ns is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns. Note 1 1 1 1 1 2,5 5 2 2 3 4 5 Page

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