PDF SM8213AM Data sheet ( Hoja de datos )

Número de pieza	SM8213AM
Descripción	POCSAG Decoder For Multiframe Pagers
Fabricantes	Nippon Precision Circuits Inc
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No Preview Available ! NIPPON PRECISION CIRCUITS INC. SM8213AM POCSAG Decoder For Multiframe Pagers OVERVIEW The SM8213AM is a POCSAG-standard (Post Ofﬁce Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommen- dation 584 concerning standard international wire- less calling codes. The SM8213AM supports call messages in either tone, numerical or character outputs at signal speeds of 512, 1200 or 2400 bps. The signal input stage fea- tures a built-in ﬁlter. Each of the addresses (max. 7 + 1 dummy = 8) can be assigned to any frame, which also makes the device conﬁgurable for many additional services. Each address can be independently set to ON/OFF. Furthermore, built-in buffer memory means decoded information can be fetched in sync with the micro- controller clock, thereby reducing the microcontrol- ler CPU time required. Intermittent-duty method (battery saving (BS) method) control signals, com- patible with PLL operation, and Molybdenum-gate CMOS structure makes possible the construction of low-voltage operation, low power dissipation sys- tems. The SM8213AM is available in 16-pin SSOPs. FEATURES s Conforms to POCSAG standard for pagers s 512, 1200 or 2400 bps signal speed s Multiframe compatible (each address individually controllable) s 8 addresses × 4 sub-addresses (total of 32 addresses) control (8 addresses comprise 7 actual addresses + 1 dummy address) s Built-in buffer memory (1 code word) s Supports tone, numeric or character call messages s Built-in input signal ﬁlter, with ﬁlter ON/OFF and 4 selectable ﬁlter characteristics s PLL-compatible battery saving method (BS1, BS2, BS3 outputs) s BS1 (RF control main output signal) 61-step setup time setting s BS3 (PLL setup signal) 61-step setup time setting s BS2 (RF DC-level adjustment signal) before/dur- ing reception selectable adjustment timing s 1-bit and 2-bit burst error auto-correction function s 25 to 75% duty factor signal coverage s 8 rate error detection condition settings s 76.8 kHz system clock (crystal oscillator) s 76.8 or 38.4 kHz clock output pin s Built-in oscillator capacitor and feedback resistor s 2.0 to 3.5 V operating supply voltage s Molybdenum-gate CMOS process realizes low power dissipation s 16-pin SSOP PINOUT Top View BS1 BS2 BS3 SIGNAL XVSS XT XTN VSS 1 8 16 VDD ATTN SDI SDO SCK AREA RSTN 9 CLKO PACKAGE DIMENSIONS Unit: mm 0.6TYP 6.8 0.3 0.36 0.1 0.8 0.15+- 0.10 0.05 0 10 0.4 0.2 NIPPON PRECISION CIRCUITS—1 1 page SM8213AM AC Characteristics Recommended operating conditions unless otherwise noted Parameter Symbol Condition XT clock frequency XT clock duty cycle SCK clock pulsewidth SCK clock interval (except WRITE mode) SCK clock interval (WRITE mode) SDI data setup time SDI data hold time SDO data setup time SDO data hold time ATTN data setup time ATTN data hold time CLKO clock rise time CLKO clock fall time CLKO clock delay time RSTN pulsewidth fCYXT DXT tPWSC tCYSC tCYSC tSSDI tHSDI tSSDO tHSDO tSATT tHATT tRCLK tFCLK DCLKO tPWRS 512 bps 1200 bps 2400 bps No load No load min −250 ppm 25 2 5 5 5 5 1 1 3 – 0 1 – – – 1 Rating typ 76.8 – – – – – – – – – – – – – – – – max +250 ppm 75 150 1900 830 415 830 – – – 0 – – 500 500 1 – Unit kHz % µs µs µs µs µs µs µs µs µs ns ns µs ms Parameter/address set timing ATTN SCK SDI tHATT tPWSC 1 tSSDI tHSDI INPUT DATA 1 tCYSC 2 INPUT DATA 2 3 INPUT DATA 3 32 INPUT DATA 32 1/ 2VDD Auxiliary operating mode set timing ATTN SCK SDI Decoder Mode tHATT tPWSC 1 tSSDI tHSDI Decoder Setting1 2 Decoder Setting 2 tCYSC Current Mode START command : 66 bit time max Others : 2 bit time max 8 1/ 2VDD Decoder Setting 8 Next Mode NIPPON PRECISION CIRCUITS—5 5 Page SM8213AM Operating Modes The SM8213AM has four operating modes—Power- ON (Write), Preamble, Idle and Lock modes. Power-ON mode After power is applied, the internal registers should be reset using RSTN. When ATTN goes HIGH, the decoder sends a write request for a decoder set read command and then waits for the microcontroller (decoder set write com- mand timing starts approximately 50 ms after reset, but you should allow at least 900 ms for the oscilla- tor internal to start and stabilize). The internal opera- tion in write mode takes place at the same timing as for 1200 bps speed mode. Write data is prepared in 32-bit batches of 1 parame- ter batch and 8 address data batches for a total of 9 batches. Ensure that there are not multiple writes requests to turn ON the same address. Also, allow a minimum of 1.67 ms after transferring each command or data before issuing the next processing command. The parameter and address set commands are pro- cessed in sync with the decoder internal clock (1200 Hz). As a consequence, a gap of 28.4 ms minimum should be left between batches to provide time for processing. Alternatively, data can be written by ﬁrst using the decoder set read command to conﬁrm whether or not processing is still in progress (BUSY) before writing each batch. If the time gap is 28.4 ms or greater, conﬁrmation (READY) is not required. After parameters and all addresses have been written and after decoder processing, the decoder set start command transfers operation from write mode and starts preamble mode operation. When setting parameters and addresses in write mode, the SCK clock frequency should not be less than 1200 Hz. If this occurs, the SCK counter is rein- itialized. This function, however, does make restor- ing operation easy even if this or another clock is accidentally input. In write mode, after power is applied and after reset initialization, all 9 batches (1 parameter and 8 address batches) should be set. If not all batches are set, subsequent operation may become unstable. RSTN SCK SDI SDO BUSY WRITE MODE PREAMBLE MODE 1 ms min READ DAT A READY READ READ DAT A BUSY READY START max 900ms max. 1.67ms max. 28.4ms 129ms max : 8-bit unit time clock : 8-bit unit time data : 8-bit unit time indeterminate data 129ms max D A T A : 32-bit unit time parameter/address data Refer to the AC Characteristics section for detailed timing specifications. Figure 4. Power-ON mode timing NIPPON PRECISION CIRCUITS—11 11 Page

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