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PDF XRT71D00 Data sheet ( Hoja de datos )
| Número de pieza | XRT71D00 | |
| Descripción | E3/DS3/STS-1 JITTER ATTENUATOR/STS-1 TO DS3 DESYNCHRONIZER | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER
JULY 2000
REV. 1.01
GENERAL DESCRIPTION
The XRT71D00 is a single channel, single chip Jitter
Attenuator, that meets the Jitter requirements speci-
fied in the ETSI TBR-24, Bellcore GR-499 and GR-
253 standards.
In addition, the XRT71D00 also meets the Jitter and
Wander specifications described in the ANSI
T1.105.03b 1997, Bellcore GR-253 and GR-499 stan-
dards for Desynchronizing and Pointer adjustments in
the DS3 to STS-SPE mapping applications.
FEATURES
• Meets the E3/DS3/STS-1 jitter requirements
• No external components required
• Compliance with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards
• Meets output jitter requirement as specified by
ETSI TBR24
• Meets the Jitter and Wander specifications
described in T1.105.03b,GR-253 and GR-499 stan-
dards.
• Selectable buffer size of 16 and 32 bits
• Jitter attenuator can be disabled
• Available in a 32 pin TQFP package.
• Single 3.3V or 5.0V supply.
• Operates over - 400 C to 850 C temperature range.
APPLICATIONS
• E3/DS3 Access Equipment.
• STS-SPE to DS3 Mapper
• DSLAMs
BLOCK DIAGRAM OF THE XRT71D00
BWS
IC T
DJA
RC lk
C lk E S
RPOS
RNEG
Tim ing C ontrol B lock /
Phase locked Loop
W rite Clock
Read Clock
16/32 Bit FIFO
M Clk
R R C lk
RRPOS
RRNEG
FL
H O S T /H W
RST
DS3/E3
M icroprocessor Serial
In te rfa c e
CS SDI SDO SClk
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.01
PIN DESCRIPTION
PIN #
11
12
13
14
15
16
17
18
19
NAME
FSS/(SClk)
HOST/HW
NC
FL
BWS/
Ch_Addr_1
NC
NC
DJA/
(SDO)
RST
TYPE
I
I
***
O
I
***
***
I/(O)
I
DESCRIPTION
FIFO Size Select Input/Serial Clock Input.
The function of this depends on whether XRT71D00 is configured in Hard-
ware or Host mode.
Hardware Mode—FIFO Size Select Input
When high: Selects 32 bits FIFO.
When low: Selects 16 bits FIFO.
Host Mode—Microprocessor Serial Interface Clock Signal
This signal will be used to (1) sample the data, on the SDI pin, on the rising
edge of this signal. Additionally, during “Read” operations, the Micropro-
cessor Serial Interface will update the SDO output on the falling edge of
this signal.
Host/Hardware Mode Select:
An active-high input enables the Host mode. Data is written to the com-
mand registers to configure the XRT71D00.
In the Host mode, the states of discrete input pins are inactive.
An active-low input enables the Hardware Mode.In this mode, the discrete
inputs are active.
This pin is not connected internally.
FIFO Limit.
This output pin is driven high whenever the internal FIFO comes within
two-bits of being completely full.
Bandwidth Select Input/Channel Addr_1 Assignment Input.
The function of this input pin depends on whether XRT71D00 is configured
in Host or Hardware mode.
Hardware Mode—Bandwidth Select Input:
Connect this pin high to select wide jitter transfer bandwidth, and connect
low to select narrow jitter transfer bandwidth.
Host Mode—Channel_Addr_1 Assignment Input:
This input pin, along with pin 28 permits the user to assign a “Channel
Address” to the XRT71D00 device.
This pin is not connected internally.
This pin is not connected internally.
Disable Jitter Attenuator Input/Serial Data Output pin:
The function of this pin depends on whether XRT71D00 is configured in
Host or Hardware mode.
Hardware Mode—Disable Jitter Attenuator:
An active-high disables the Jitter Attenuator.The RPOS/RNEG and RClk
will be passed through without jitter attenuation.
Host Mode—Serial Data Output:
This pin will serially output the contents of the specified Command Regis-
ter, during “Read” Operations. The data, on this pin, will be updated on the
falling edge of the SClk input signal. This pin will be tri-stated upon com-
pletion of data transfer.
NOTE: The user is advised to tie this pin to GND, if the XRT71D00 has
been configured to operate in the “HOST” Mode.
Reset Input. (Active-Low)
A high-low transition will re-center the internal FIFO, and will clear the
Command Registers (for Host Mode operation). Resetting this pin may
corrupt data within the device.
For normal operation, pull this pin to VDD.
5
5 Page 
XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER
REV. 1.01
FIGURE 3. CATEGORY 1 DS3 JITTER TRANSFER MASK
0.1
Acceptable
Range
slope = -20 dB/decade
40
Frequency (Hz)
JITTER TOLERANCE:
The jitter tolerance in the network element is defined
as the maximum amount of jitter in the incoming sig-
nal that it can receive in an “error-free”manner.
JITTER GENERATION:
Jitter generation is defined in Section 7.3.3 of GR-
499-CORE. Jitter generation criteria exists for both
Category I and II interfaces, which consist of “map-
ping” and “pointer adjustment” jitter generation.
Mapping jitter is the sum of the intrinsic payload map-
ping jitter and the jitter that is generated as a result of
the bit stuffing mechnisms used in all of the asynchro-
nous DSn mapping into STS SPE.
JITTER ATTENUATION:
A digital Jitter Attenuation loop combined with the
FIFO provides Jitter attenuation. The Jitter Attenuator
requires no external components except for the refer-
ence clock.
Data is clocked into the FIFO with the associated
clock signal (TClk or RClk) and clocked out of the
FIFO with the dejittered clock and data. When the
FIFO is within 2 bits of being completely full, the FIFO
Limit (FL) will be set.
In Figure 1 and Figure 2, this “de-jittered” clock is la-
beled “Smoothed Clock”. This “Smoothed Clock” is
now used to “Read Out” the “Recovered Data” from
the 16/32 bit FIFO. This “Smoothed Clock” will also
be output to the Terminal Equipment via the “RRClk”
output pin. Likewise, the “Smoothed Recovered Data”
will output to the Terminal Equipment via the RRPOS
and RRNEG output pins.
The XRT71D00 device is designed to work as a com-
panion device with XRT7300 (STS-1/DS3/E3) Line
Interface Unit.
.ETSI TBR24 specifies the maximum output jitter in
loop timing must be no more than 0.4UIpp when mea-
sured between 100Hz to 800KHzwith upto 1.5UI input
jitter at 100Hz.. This means a jitter attenuator with
bandwidth less than 100Hz is required to be compli-
ant with the standard. ITU G.751 is another applica-
tion where low bandwidth jitter attenuator is needed
to smooth the gapped clock output in the de-multi-
plexer system.
SONET STS-1 DS3 MAPPING:
Bellcore GR-253 section 3.4.2 and the ANSI T1.105-
199 describes the asynchronous mapping for DS3 in-
to STS-1 SPE.
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet XRT71D00.PDF ] | |
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