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PDF TFRA08C13 Data sheet ( Hoja de datos )
| Número de pieza | TFRA08C13 | |
| Descripción | TFRA08C13 OCTAL T1/E1 Framer | |
| Fabricantes | Agere Systems | |
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Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Features
s Eight independent T1/E1 transmit and receive
framers.
s Internal DS1 transmit clock synthesis—no external
oscillator necessary.
s Comprehensive alarm reporting and performance
monitoring:
— Programmable automatic and on-demand alarm
transmission.
s Automatic facility data link:
— Automatic transmission of ESF performance
report message.
s Common 2.048 Mbits/s, 4.096 Mbits/s, or
8.192 Mbits/s TDM highway.
s Dual- or single-rail line-side I/O.
s Supports one second polling interval for perfor-
mance monitoring.
s IEEE * Std. 1149.1 JTAG boundary scan.
s 3.3 V low-power CMOS with 5 V tolerant inputs.
s Available in 352-pin PBGA.
T1/E1 Framer Features
s Supports T1 framing modes ESF, D4, SLC ®-96,
T1DM DDS.
s Supports G.704 basic and CRC-4 multiframe for-
mat E1 framing and procedures consistent with
G.706.
s Supports unframed transmission format.
s T1 signaling modes: transparent; ESF 2-state,
4-state, and 16-state; D4 2-state and 4-state;
SLC-96 2-state, 4-state, 9-state, and 16-state. E1
signaling modes: transparent and CAS.
s Alarm reporting and performance monitoring per
AT&T, ANSI †, and ITU-T standards.
s Programmable, independent transmit and receive
system interfaces at a 2.048 MHz, 4.096 MHz, or
8.192 MHz data rate.
Facility Data Link Features
s HDLC or transparent mode.
s Automatic transmission of the ESF performance
report messages (PRM).
s Detection of the ESF PRM.
s Detection of the ANSI ESF FDL bit-oriented codes.
s 64-byte FIFO in both transmit and receive direc-
tions.
s Programmable FIFO full and empty level interrupt.
s User-programmable microprocessor interface.
Microprocessor Interface
s 33 MHz read and write access.
s 12-bit address, 8-bit data interface.
s Intel ‡ or Motorola§ style control interfaces.
s Directly addressable internal registers.
s Programmable interrupts.
Applications
s DS3 and E3 port cards for narrowband DXCs.
s Multiservice switches.
s High density DS1 and E1 port cards.
s Frame relay access devices.
s Byte-synchronous SDH/SONET mapping.
s SONET and SDH drop alignment.
s IP and packet routers.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
† ANSI is a registered trademark of American National Standards
Institute, Inc.
‡ Intel is a registered trademark of Intel Corporation.
§ Motorola is a registered trademark of Motorola, Inc.
1 page  
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Table of Contents (continued)
Figures
Page
Figure 29. 20-Stage Shift Register Used to Generate the Quasi-Random Signal ..................................................78
Figure 30. 15-Stage Shift Register Used to Generate the Pseudorandom Signal ..................................................79
Figure 31. TFRA08C13 Facility Data Link Access Timing of the Transmit and Receive Framer Sections ..............84
Figure 32. Block Diagram for the Receive Facility Data Link Interface....................................................................85
Figure 33. Block Diagram for the Transmit Facility Data Link Interface ...................................................................90
Figure 34. Local Loopback Mode ............................................................................................................................95
Figure 35. Remote Loopback Mode ........................................................................................................................96
Figure 36. TFRA08C13 Phase Detector Circuitry ...................................................................................................97
Figure 37. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0—bit 2 = 100 (Binary)) ..........101
Figure 38. CHIDTS Mode Concentration Highway Interface Timing .....................................................................102
Figure 39. Associated Signaling Mode Concentration Highway Interface Timing .................................................103
Figure 40. CHI Timing with ASM and CHIDTS Enabled .......................................................................................103
Figure 41. TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 0
(CEX = 3 and CER = 4, Respectively) ...............................................................................................................104
Figure 42. Receive CHI (RCHIDATA) Timing.........................................................................................................105
Figure 43. Transmit CHI (TCHIDATA) Timing ........................................................................................................105
Figure 44. Block Diagram of the TFRA08C13's Boundary-Scan Test Logic .........................................................106
Figure 45. BS TAP Controller State Diagram ........................................................................................................107
Figure 46. Mode 1—Read Cycle Timing (MPMODE = 0) .....................................................................................116
Figure 47. Mode 1—Write Cycle Timing (MPMODE = 0)......................................................................................116
Figure 48. Mode 3—Read Cycle Timing (MPMODE = 1) .....................................................................................117
Figure 49. Mode 3—Write Cycle Timing (MPMODE = 1)......................................................................................117
Tables
Page
Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order.......................................................................16
Table 2. Pin Descriptions........................................................................................................................................18
Table 3. AMI Encoding ...........................................................................................................................................31
Table 4. DS1 ZCS Encoding...................................................................................................................................32
Table 5. DS1 B8ZS Encoding.................................................................................................................................32
Table 6. ITUHDB3 Coding ......................................................................................................................................33
Table 7. T-Carrier Hierarchy....................................................................................................................................34
Table 8. D4 Superframe Format .............................................................................................................................36
Table 9. DDS Channel-24 Format ..........................................................................................................................37
Table 10. SLC-96 Data Link Block Format .............................................................................................................38
Table 11. SLC-96 Line Switch Message Codes .....................................................................................................39
Table 12. Transmit and Receive SLC-96 Stack Structure.......................................................................................39
Table 13. Extended Superframe (ESF) Structure...................................................................................................40
Table 14. T1 Loss of Frame Alignment Criteria ......................................................................................................41
Table 15. T1 Frame Alignment Procedures ............................................................................................................42
Table 16. Robbed-Bit Signaling Options.................................................................................................................43
Table 17. SLC-96 9-State Signaling Format ...........................................................................................................43
Table 18.16-State Signaling Format .......................................................................................................................44
Table 19. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame ......................................................46
Table 20. ITU CRC-4 Multiframe Structure.............................................................................................................49
Table 21. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure ........................................55
Table 22. Transmit and Receive Sa Stack Structure...............................................................................................59
Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames ...........................................62
Table 24. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels....................................62
Lucent Technologies Inc.
5
5 Page 
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
Functional Description
Note: The Concentration Highway Interface Specification, Lucent Technologies Microelectronics Group November
1990 (DS90-124SMOS) defines the transmit path as output to the system interface, and the receive path
as input from the system interface. This document is consistent with that definition.
RPD[1—8]
RND_RBPV[1—8]
RLCK[1—8]
RECEIVE
CHANNEL [1—8]
DECODER
RECEIVE
FRAMER
UNIT
RECEIVE
ELASTIC STORE
(2 FRAMES)
TRANSMIT
CONCENTRATION
HIGHWAY
INTERFACE
(TCHI)
TND[1—8],
TPD[1—8],
TLCK[1—8]
RECEIVE FACILITY
DATA LINK MONITOR
(HDLC OR
TRANSPARENT
FRAMING)
RECEIVE
SIGNALING UNIT
(DS1: ROBBED-BIT
OR
CEPT: TS16)
CHICK
RLCK
RECEIVE
CHANNEL DIGITAL
PHASE DETECTOR
TRANSMIT
CHANNEL [1—8]
TRANSMIT FACILITY
DATA LINK MONITOR
(HDLC OR
TRANSPARENT
FRAMING)
TRANSMIT
SIGNALING UNIT
(DS1: ROBBED-BIT
OR
CEPT: TS16)
CHICK
TRANSMIT
CHANNEL DIGITAL
PHASE DETECTOR
ENCODER
XMIT FRAMER
TCLK
SYNTHESIZER
TRANSMIT
FRAMER
UNIT
TRANSMIT
ELASTIC STORE
(2 FRAMES)
RECEIVE
CONCENTRATION
HIGHWAY
INTERFACE
(RCHI)
MICROPROCESSOR INTERFACE
CHICK
CHIFS
TCHIDATA[1—8]
TCHIDATAB[1—8]
RFRMCK[1—8],
RFRMDATA[1—8],
RFS[1—8]
RFDL[1—8], RFDLCK[1—8]
DIV-RLCK, DIV-CHICK,
CHICK-EPLL
PLLCK[1—8]
DIV-PLLCK, DIV-CHICK,
PLLCK-EPLL
TFDL[1—8], TFDLCK[1—8]
RCHIDATA_A[1—8]
RCHIDATA_B[1—8]
TFS[1—8]
MPMODE
A[11:0]
D[7:0]
CS ALE_AS
RD_R/W WR_DS
RDY_DTACK INTERRUPT MPCK
Figure 1. TFRA08C13 Block Diagram (One of Eight Channels)
5-6937(F)r.4
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11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TFRA08C13.PDF ] | |
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