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PDF CY7C144 Data sheet ( Hoja de datos )
| Número de pieza | CY7C144 | |
| Descripción | 8K x 9/0 Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C144 CY7C1458K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
CY7C145
CY7C144
Features
• True Dual-Ported memory cells which allow
simultaneous reads of the same memory location
• 8K x 8 organization (CY7C144)
• 8K x 9 organization (CY7C145)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15ns
• Low operating power: ICC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Master/Slave select pin allows bus width expansion to
16/18 bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
Functional Description
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
are included on the CY7C144/5 to handle situations when mul-
tiple processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C144/5
can be utilized as a standalone 64/72-Kbit dual-port static
RAM or multiple devices can be combined in order to function
as a 16/18-bit or wider master/slave dual-port static RAM. An
M/S pin is provided for implementing 16/18-bit or wider mem-
ory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags,
BUSY and INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip enable (CE) pin or SEM pin.
Logic Block Diagram
R/W L
CE L
OEL
R/W R
CE R
OER
(7C145) I/O8L
I/O7L
I/O0L
BUSYL [1, 2]
A 12L
A 0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
I/O 8R(7C145)
I/O 7R
I/O 0R
BUSYR[1, 2]
A 12R
A 0R
SEM L
INT L [2]
CEL
OEL
R/W L
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
INTERRUPT
SEMAPHORE
ARBITRATION
M/S
CE R
OE R
R/W R
SEM R
INT R[2]
C144-1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06034 Rev. *B
Revised June 22, 2004
1 page  
CY7C145
CY7C144
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 4.0 mA
VIH Input HIGH Voltage
VIL Input LOW Voltage
IIX
Input Leakage Current
GND < VI < VCC
IOZ Output Leakage Current Outputs Disabled, GND < VO < VCC
ICC
Operating Current
VCC = Max., IOUT = 0 mA
Com’l
Outputs Disabled
Ind
ISB1
Standby Current
(Both Ports TTL Levels)
Cf =ELfMaAnXd[8C] ER > VIH,
Com’l
Ind
ISB2
Standby Current
(One Port TTL Level)
Cf =ELfMoArXC[8E] R > VIH,
Com’l
Ind
ISB3 Standby Current
Both Ports
Com’l
(Both Ports CMOS Levels) CE and CER > VCC – 0.2V,
Ind
VorINV>INV<C0C.2–V0, .f2=V0[8]
ISB4 Standby Current
One Port
Com’l
(One Port CMOS Level)
CEL or CER > VCC – 0.2V,
VIN > VCC – 0.2V or
Ind
VPIoNrt<O0u.2tpVu,tAs,cfti=vefMAX[8]
7C144-35
7C145-35
Min. Max.
2.4
0.4
2.2
0.8
−10 +10
−10 +10
160
180
30
40
100
110
15
30
7C144-55
7C145-55
Min. Max.
2.4
0.4
2.2
0.8
−10 +10
−10 +10
160
180
30
40
100
110
15
30
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
90 90 mA
100 100
Capacitance[9]
Parameter
Description
Test Conditions
CIN
COUT
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Note:
9. Tested initially and after any design or process changes that may affect these parameters.
Max.
10
15
Unit
pF
pF
Document #: 38-06034 Rev. *B
Page 5 of 20
5 Page 
CY7C145
CY7C144
Switching Waveforms (continued)
Read with BUSY (M/S=HIGH)[21]
ADDRESSR
R/WR
DATAINR
ADDRESSL
tPS
tWC
MATCH
tPWE
tSD
VALID
MATCH
tHD
BUSYL
DATA OUTL
tBLA
Write Timing with Busy Input (M/S=LOW)
tDDD
tBHA
tBDD
tWDD
R/W
tPWE
BUSY
tWB tWH
VALID
C144–17
C144–18
Document #: 38-06034 Rev. *B
Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CY7C144.PDF ] | |
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