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PDF IDT82V1671 Data sheet ( Hoja de datos )
| Número de pieza | IDT82V1671 | |
| Descripción | CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT (RSLIC) & QUAD PROGRAMMABLE PCM CODEC | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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CHIPSET OF RINGING SUBSCRIBER
LINE INTERFACE CIRCUIT (RSLIC) &
QUAD PROGRAMMABLE PCM CODEC
PRELIMINARY
IDT82V1671 (RSLIC)
IDT82V1074 (CODEC)
FEATURES
• Programmable DC feeding characteristics
• Programmable digital filters adapting to different requirements:
− Impedance matching
− Transhybrid balance
− Transmit and receive gain adjustment
− Frequency response correction
• Off-hook and ground-key detection
• AC/DC ring trip detection
• Programmable internal balanced ringing without external
components
• Supports external ringing
• Selectable MPI and GCI interfaces
• Supports A/µ-law compressed and linear data formats
• Programmable IO pins with relay-driving or analog input
capability
• Line polarity reversal
• Integrated FSK generator for sending Caller ID information
• On-hook transmission
• 2 programmable tone generators per channel
• Integrated Universal Tone Detection (UTD) unit for fax/modem
tone detection
• Integrated Test and Diagnosis Functions (ITDF)
• Three-party conference
• Only battery and 3.3 V power supply needed
• Package available:
IDT82V1671: 28 pin PLCC
IDT82V1074: 100 pin TQFP
DESCRIPTION
The RSLIC-CODEC chipset is comprised of one four-channel
programmable PCM CODEC (IDT82V1074) and four single-channel
ringing SLICs (IDT82V1671). The chipset provides a total solution for
line card designs. In addition to providing a complete software
programmable solution for BORSCHT, additional functions such as FSK
generator, Universal Tone Detection (UTD) unit, tone generators, ringing
generator, Integrated Test and Diagnosis Functions (ITDF), line polarity
reversal and three-party conference are integrated in to the chipset. The
high integration of system functions reduces board space requirements
of the line card and saves cost.
The chipset is fully programmable via a Microprocessor Interface
(MPI) or a General Circuit Interface (GCI). In both MPI and GCI modes,
the chipset supports A/µ-law companding format or linear data format.
Programmable digital filters on the chipset provide the necessary
transmit and receive filtering to realize impedance matching, transhybrid
balance, frequency response correction and transmit/receive gains
adjustment. The full programmability optimizes the performance of line
card products and allows one line card to adapt to different requirements
worldwide.
The powerful Integrated Test and Diagnosis Functions (ITDF)
accomplish necessary tests and measurements without external test
equipment or relays. This brings convenience to system maintenance
and diagnosis.
This chipset can be used in digital telecommunication applications
such as VoIP, VoATM, PBX, CO and DLC etc.
CHIPSET FUNCTIONAL BLOCK DIAGRAM
Telephone
Telephone
Telephone
Telephone
Protection
Circuit
Protection
Circuit
Protection
Circuit
Protection
Circuit
RSLIC
1#
RSLIC
2#
RSLIC
3#
RSLIC
4#
CODEC
Level
Metering
Off-hook
Detection
MPI
Interface
DC Feed
DSP
PCM/GCI
Interface
Filtering
Self Test
CID
UTD
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
2003 Integrated Device Technology, Inc.
1
Microprocessor
PCM/GCI
APRIL 22, 2003
DSC-6042/2
1 page  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET
INDUSTRIAL TEMPERATURE RANGE
3.9.4.2 Level Meter Gain Filter and Rectifier ..........................................................................................................................40
3.9.4.3 Level Meter Integrator ................................................................................................................................................41
3.9.4.4 Level Meter Result Register .......................................................................................................................................42
3.9.4.5 Level Meter Shift Factor .............................................................................................................................................42
3.9.4.6 Level Meter Threshold Setting....................................................................................................................................42
3.9.5 Measurement via AC Level Meter ..............................................................................................................................................44
3.9.5.1 Current Measurement via VTAC.................................................................................................................................44
3.9.5.2 AC Level Meter Operational State Flow .....................................................................................................................44
3.9.6 Measurement via DC Level Meter..............................................................................................................................................44
3.9.6.1 Offset Current Measurement ......................................................................................................................................44
3.9.6.2 Leakage Current Measurement..................................................................................................................................44
3.9.6.3 Loop Resistance Measurement..................................................................................................................................45
3.9.6.4 Line Resistance Tip/GND and Ring/GND...................................................................................................................45
3.9.6.5 Capacitance Measurement.........................................................................................................................................46
3.9.6.6 Voltage Measurement ................................................................................................................................................47
3.9.6.7 Voltage Offset Measurement......................................................................................................................................48
3.9.6.8 Ring Trip Operational Amplifier Offset Measurement.................................................................................................48
4 Interface ............................................................................................................................................................................................................49
4.1 PCM/MPI Interface ..................................................................................................................................................................................49
4.1.1 MPI Control Interface .................................................................................................................................................................49
4.1.2 PCM Interface ............................................................................................................................................................................50
4.1.2.1 PCM Clock Configuration ...........................................................................................................................................50
4.1.2.2 Time Slot Assignment.................................................................................................................................................51
4.1.2.3 PCM Highway Selection .............................................................................................................................................51
4.2 GCI Interface ...........................................................................................................................................................................................51
4.2.1 Compressed GCI Mode..............................................................................................................................................................51
4.2.2 Linear GCI Mode ........................................................................................................................................................................51
4.2.3 Command/Indication (C/I) Channel ............................................................................................................................................54
4.2.3.1 Downstream C/I Channel Byte ...................................................................................................................................54
4.2.3.2 Upstream C/I Channel Byte........................................................................................................................................54
4.2.4 GCI Monitor Transfer Protocol....................................................................................................................................................55
4.2.4.1 Monitor Channel Operation ........................................................................................................................................55
4.2.4.2 Monitor Handshake Procedure...................................................................................................................................55
4.3 Analog POTS Interface............................................................................................................................................................................57
4.4 RSLIC and CODEC Interface ..................................................................................................................................................................57
5 Programming....................................................................................................................................................................................................58
5.1 Overview..................................................................................................................................................................................................58
5.1.1 MPI Programming ......................................................................................................................................................................58
5.1.1.1 Broadcast Mode for MPI Programming ......................................................................................................................58
5.1.1.2 Identification Code for MPI Programming...................................................................................................................58
5.1.2 GCI Programming ......................................................................................................................................................................58
5.1.2.1 Program Start Byte for GCI Programming..................................................................................................................58
5.1.2.2 Identification Command for GCI Programming...........................................................................................................58
5.2 Register/RAM Commands.......................................................................................................................................................................58
5.2.1 Register/RAM Command Format ...............................................................................................................................................58
5.2.2 Addressing the Local Registers..................................................................................................................................................58
5.2.3 Addressing the Global Registers................................................................................................................................................59
5.2.4 Addressing the FSK-RAM ..........................................................................................................................................................59
5.2.5 Addressing the Coe-RAM...........................................................................................................................................................60
5.3 Registers Description ..............................................................................................................................................................................62
5.3.1 Registers Overview ....................................................................................................................................................................62
5.3.2 Global Registers List ..................................................................................................................................................................64
5.3.3 Local Registers List ....................................................................................................................................................................72
5.4 Programming Examples ..........................................................................................................................................................................82
5.4.1 Programming Examples for MPI Mode.......................................................................................................................................82
5.4.1.1 Example of Programming the Local Registers via MPI ..............................................................................................82
5
5 Page 
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET
INDUSTRIAL TEMPERATURE RANGE
2 PIN DESCRIPTIONS
2.1 RSLIC PIN DESCRIPTION
Name
VBH
RIS
BGND
TIS
VDD
AGND
CF
VCM
ACN
ACP
DCN
DCP
VTAC
CA
VTDC
VL
CB
M3
M2
M1
CS
RT
RSN
RSP
VCMB
RING
TIP
VBL
Type
Power
−
Power
−
Power
Power
Ο
I
I
I
I
I
O
−
O
O
−
I/O
I
I
I
O
I
I
O
I/O
I/O
Power
Pin Number
Description
1 Negative battery supply (−70 V ≤ VBH ≤ −52 V)
2
Ring sense, connected to the RING pin through an external resistor RS. Refer to “8 Application Circuits” on page 103
for details.
3 Battery ground. This pin should be externally connected to AGND.
4 Tip sense, connected to the TIP pin through an external resistor RS.
5 +3.3 V power supply.
6 Analog ground. This pin should be externally connected to BGND.
7
Output voltage of VBAT/2 (VBAT represents the selected battery voltage VBH or VBL). An external capacitor is
connected between this pin and the ground for filtering.
8 Reference voltage input, typical 1.5 V.
9 Differential AC voltage, negative.
10 Differential AC voltage, positive.
11 Differential DC voltage, negative.
12 Differential DC voltage, positive.
13 Sense transversal AC voltage.
14
External capacitor connection. An external capacitor is connected between this pin and the CB pin to separate the DC
component from the sense transversal voltage.
15 Sense transversal DC voltage.
16 Sense longitudinal voltage.
17
External capacitor connection. An external capacitor is connected between this pin and the CA pin to separate the DC
component from the sense transversal voltage.
18
Mode control input 3 or temperature information output.
The logic level of the CS pin determines the direction of the M3 pin. See the description of the CS pin for details.
19 Mode control input 2. This is a binary logic pin, together with M1 and M3, controlling the operating mode of the RSLIC.
20 Mode control input 1. This is a binary logic pin, together with M2 and M3, controlling the operating mode of the RSLIC.
Chip select input. It is a ternary logic pin.
When the CS pin is logic 0 (0 V< CS < 0.8 V), the RSLIC receives the mode control data from the CODEC through
the M1 to M3 pins.
21 When the CS pin is logic 1 (2.2 V< CS < 3.3 V), the RSLIC sends the temperature information of itself to the
CODEC through the M3 pin.
When the CS pin is 1.5 V (with ±0.5 V tolerance), the RSLIC neither receives the data from the CODEC nor sends
temperature information to it.
22 Ring trip operational amplifier output.
23 Negative ring trip operational amplifier input.
24 Positive ring trip operational amplifier input.
25 VCM buffer output, 1.5 V, used for external ringing mode.
26 Subscriber loop connection Ring.
27 Subscriber loop connection Tip.
28 Negative battery supply (−52 V ≤ VBL ≤ −20 V).
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT82V1671.PDF ] | |
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