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PDF SY89824L Data sheet ( Hoja de datos )
| Número de pieza | SY89824L | |
| Descripción | 3.3V 1:22 HIGH-PERFORMANCE / LOW VOLTAGE BUS CLOCK DRIVER | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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3.3V 1:22 HIGH-PERFORMANCE,
LOW VOLTAGE
BUS CLOCK DRIVER
ClockWorks™
SY89824L
FEATURES
DESCRIPTION
s 3.3V core supply, 1.8V output supply for reduced
power
s LVPECL and HSTL inputs
s 22 differential HSTL (low-voltage swing) output pairs
s HSTL outputs drive 50Ω to ground with no offset
voltage
s Low part-to-part skew (200ps max.)
s Low pin-to-pin skew (50ps max.)
s Available in a 64-Pin EPAD HQFP
PIN CONFIGURATION
VCCO
NC
NC
VCCI
HSTL_CLK
HSTL_CLK
CLK_SEL
LVPECL_CLK
LVPECL_CLK
GND
OE
NC
NC
Q21
Q21
VCCO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 64-PIN
9 HQFP
10
41
40
39
11 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCCO
Q7
Q7
Q8
Q8
Q9
Q9
Q10
Q10
Q11
Q11
Q12
Q12
Q13
Q13
VCCO
The SY89824L is a High Performance Bus Clock Driver
with 22 differential HSTL (High Speed Transceiver Logic)
output pairs. The part is designed for use in low voltage
(3.3V/1.8V) applications which require a large number of
outputs to drive precisely aligned, ultra low skew signals to
their destination. The input is multiplexed from either HSTL
or LVPECL (Low Voltage Positive Emitter Coupled Logic)
by the CLK_SEL pin. The Output Enable (OE) is
synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.
The SY89824L features low pin-to-pin skew (50ps max.)
and low part-to-part skew (200ps max.)—performance
previously unachievable in a standard product having such
a high number of outputs. The SY89824L is available in a
single space saving package, enabling a lower overall cost
solution.
PIN NAMES
Pin
HSTL_CLK, /HSTL_CLK
LVPECL_CLK, /LVPECL_CLK
CLK_SEL
OE
Q0-Q21, /Q0-/Q21
GND
VCCI
VCCO
Function
Differential HSTL Inputs
Differential LVPECL Inputs
Input CLK Select (LVTTL)
Output Enable (LVTTL)
Differential HSTL Outputs
Ground
VCC Core
VCC Output
APPLICATIONS
s High-performance PCs
s Workstations
s Parallel processor-based systems
s Other high-performance computing
s Communications
LOGIC SYMBOL
CLK_SEL
HSTL_CLK
HSTL_CLK
0
LVPECL_CLK
LVPECL_CLK
OE
1
1
22
Q0 - Q21
22
Q0 - Q21
LEN
Q
D
Rev.: C Amendment: /1
Issue Date: March 2000
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet SY89824L.PDF ] | |
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