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PDF HT82V842 Data sheet ( Hoja de datos )
| Número de pieza | HT82V842 | |
| Descripción | CCD CDS/PGA/10b-20M-ADC | |
| Fabricantes | Holtek Semiconductor | |
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HT82V842
CCD CDS/PGA/10b-20M-ADC
Features
· Operating voltage: 2.7V~3.6V
· Low power consumption: 70mW (Typ.)
· Power down mode: less than 30mW
· Accepts a direct signal input to ADC or PGA at 1.0
VPP (Typ.)
· CCD signal input level: 1.1 VP-P (Max.)
· 10-bit ADC (up to 20MHz)
- DNL: ±0.6 LSB (Typ.)
· Black level neutralizer, target setting: 16~127LSB
· Built-in serial interface
· Independent ADC input conversion clock and data
output clock
· Independent CDS and PGA gain control
- CDS: -1.94/0/6/12dB
- PGA: 0~24dB
· Wide gain range: -1.94~36dB
· High speed sample and hold circuit: pulse width 11ns
(Min.)
· 48-pin LQFP package
General Description
The HT82V842 is a CMOS single-chip signal process-
ing device for CCD area sensors. It consists of a clamp
circuit, Correlated Double Sampler (CDS), Programma-
ble Gain Amplifier (PGA), reference voltage generator,
black level detection circuit, 20MHz 10-bit A/D converter
(ADC), timing generator for internally required pulses,
serial interface for internal function control and PGA
gain control.
Block Diagram
O B P C C D C LP A D C LP
C S SC K SD ATA
M ONOUT
ADCK
B LK
C LP C A P
T im in g
G e n e ra to r
D C C la m p
S e r ia l
R e g is te r
B andG ap
C ir c u it
R E F IN
C C D IN
C C D A D C LP
A D IN
O BCAP
C C D C LP
CDS
S /H
-1 .9 4 /0 /6 /1 2 d B
PG A
R ough
PG A
F in e
0~6dB
0 /6 /1 2 /1 8 d B (0 .0 4 7 d B /S te p )
1 0 - B it
ADC
DAC
O BP
C o m p a re
B la c k L e v e l
R e g is te r
VRP
VCO M
VRN
D O 0~D O 9
V DD V SS
R ESET STBY SH R SH D
O U TC K
Rev. 1.00
1 July 15, 2004
1 page  
HT82V842
Functional Description
CDS (Correlated Double Sampling) Circuit
Connect the CCDIN pin to the CCD sensor thru a capac-
itor. Connect also the REFIN pin to VSS thru a capacitor.
The CDS circuit holds the pre-charge voltage of the
CCD at SHR pulse and do sampling of the CCD pixel
data at SHD pulse. Correlated noise is removed by sub-
tracting the pre-charge voltage from the pixel data level.
CDS could choose a gain setting from 0, 6.02, 12 or
-1.94dB (Mode 3, register D4 and D5 bits). A CDS gain
is controlled by PGA gain. It is recommended to in-
crease the CDS gain then increase the PGA gain to re-
duce the noise level.
Clamp Circuits
· DC clamp
The DC level of the CCDIN/REFIN input is fixed by an
internal DC clamp circuit. The DC level of the
C-coupled CCD signal at the CDS input is set to
CLPCAP by the internal DC clamp circuit. The clamp
switches are usually turned on at the black level cali-
bration period. The CLPCAP pin connects to VSS thru
a 0.1mF capacitor.
· ADIN signal clamp
Clamp operation can also be used for the ADIN path.
The clamp voltage is different from the CCDIN/REFIN
signal and it could be turned off by register setting. At
²ADIN signal to ADC² mode, the ADCLP signal con-
trols the ²clamp circuit². Black level calibration circuit
is also controlled by ADCLP at ²ADIN signal to PGA²
mode.
· Clamp control
¨ Clamp current (Mode 2 register D7). Charge current
can select normal or fast clamp.
CCD
¨ Clamp target (Mode 2 register D5 and D4), input
signals (REFIN and CCDIN) to be clamped are
selectable. The clamp function can be turned off.
Black Level Cancel Circuit
The purpose of a black level cancel circuit is to control
the DC level of the PGA input. The ADC output code at
an optical black period may correspond to the black
level code set up by the register. A black level code of (1
to) 16 to 127 LSB is available (the default is 64 LSB).
While the OBP pin is active a black level cancel loop is
established. In the loop, a comparison is made between
the ADC output code and the black level code, the result
controls the voltage of the OBCAP capacitor. Hence, the
OBCAP voltage settles gradually and the signal level of
the optical black period corresponds to the established
value.
The following conditions will reset the OBCAP capaci-
tor:
· Set the black level reset register to ²1² (Mode 1 regis-
ter D1=1).
· Set the RESET pin to low
· Power down by STBY pin or register control
The DC clamping (CCDCLP) is allowed while the OBP
pin is low. The black level cancellation is available at
²ADIN signal to PGA² mode. The black level cancella-
tion is available at the ADCLP period in this mode. The
clamping function and black level canceling function are
done simultaneously.
ADCK
O B E ffe c tiv e P ix e l
B la n k in g
B LK
O BP
C C D C LP
O U TC K
D O 0~ D O 9
Rev. 1.00
D a ta O u tp u t
5
B la c k C o d e
July 15, 2004
5 Page 
Black level
HT82V842
Operation, ADC Code
Black Code
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Decimal
HEX
0 0 0 0 0 0 0 Forbidden
Forbidden
0 0 0 0 0 0 11
1
¯¯
¯
0 0 0 1 1 1 1 15
F
0 0 1 0 0 0 0 16
10
0 0 1 0 0 0 1 17
11
0 0 1 0 0 1 0 18
12
0 0 1 0 0 1 1 19
13
¯¯
¯
0 1 0 0 0 0 0 32
20
¯¯
¯
1 0 0 0 0 0 0 64
40
¯¯
¯
1 1 1 1 1 0 0 124
7C
1 1 1 1 1 0 1 125
7D
1 1 1 1 1 1 0 126
7E
1 1 1 1 1 1 1 127
7F
Timing Diagrams
tD R tD D
CCD
R e fe r e n c e S a m p lin g
D a ta S a m p lin g
SHR
SHD
tW R
tW D
ADCK
B LK
O BP
C C D C LP
A D C LP
O U TC K
tH O L D E
tH O L D C
D O 0~ D O 9
tP S U P
tC Y C
tH O L D
tH tL
tS U P O C
tO L
tS P
tS U P E
Rev. 1.00
11 July 15, 2004
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet HT82V842.PDF ] | |
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