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PDF CT8022 Data sheet ( Hoja de datos )
| Número de pieza | CT8022 | |
| Descripción | TELEPHONE SPEECH CIRCUIT | |
| Fabricantes | DSP Group | |
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Version: 1.18
PRELIMINARY/CONFIDENTIAL
Data
Sheet
VOIP/VON G.723.1, G729AB
TRUESPEECH® CO-PROCESSOR
System
Controller
Video
Sub-system
MODEM Data Pump
CT8022
TrueSpeech
Co-Processor
SRAM
DAA
and Phone
Interface
Microphone
&
Speaker
Interface
Phone Line
Hand/Head-set
Microphone
Speaker
CT8022 System Block Diagram
DESCRIPTION
The CT8022 is a speech co-processor which performs full-duplex speech compression and de-compression
functions. It provides speech compression for H.323 and H.324 Multimedia Visual Telephony/Video Conferencing
products and DSVD modems. The CT8022 has built-in TrueSpeech 8.5 (compatible with Microsoft Sound System
2.0, and a standard part of Microsoft Windows 95), and TrueSpeech G.723.1 (for H.323 and H.324). This
combination of ITU speech compression standards within a single device enables the creation of a single multimedia
terminal, which can operate in all types of H.324 POTS-based and H.323 LAN/Internet-based Video Conferencing
systems. TrueSpeech G.723.1 provides compressed data rates of 8.5, 6.3 and 5.3 KBPS and includes G.723.1
Annex A VAD/CNG silence compression, which can supply an even lower average bit rate. The CT8022 provides
two additional non-ITU TrueSpeech data rates at 4.8 and 4.1 KBPS. The CT8022 also supports download of
additional speech compression software modules to low-cost external memory (e.g. FlexiSpeech, G.722 and
G.729A/B). The CT8022 operates as a microprocessor peripheral device, and can co-exist with other devices such
as modem data pump and video compression chipsets. In addition, the CT8022 includes built-in Acoustical Echo
Cancellation, which complements the speech compression functions by providing concurrent hands-free operation.
The TrueSpeech G.723.1 algorithm delivers highly compressed speech without compromising the speech quality.
TrueSpeech G.723.1 at the 6.3 bit-rate has a MOS score of 3.9 for use with the ITU H.324 and H.323 standards.
CT8022A11AQC FW Revision 0118
DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
1
1 page  
Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
5 CT8022 CODEC INTERFACE ....................................................................................................................... 40
5.1 CODEC OPTIONS ........................................................................................................................................ 40
5.1.1 Master/Slave........................................................................................................................................ 41
5.1.2 8-bit A-law/µ-law and 16-bit Linear CODEC ..................................................................................... 41
5.1.3 Short or Long FSYNC......................................................................................................................... 41
5.1.4 Programmable SCLK and FSYNC Rates ............................................................................................ 41
5.1.5 Stop CODEC....................................................................................................................................... 42
6 HOST DATA TRANSFER MODES ............................................................................................................... 43
6.1 DATA TRANSFER USING THE DATA BUFFERS ..................................................................................................... 43
6.1.1 DMA Transfers ................................................................................................................................... 43
6.1.2 Host Processor Transfers..................................................................................................................... 43
6.2 DATA TRANSFER USING THE SOFTWARE CONTROL AND STATUS REGISTERS ............................................... 44
6.2.1 Host Control/Status Register Data Transfer Synchronization Modes.................................................. 44
6.3 DATA TRANSFER OPTIONS SUMMARY ......................................................................................................... 46
7 PLAY & RECORD DELAY MANAGEMENT ............................................................................................. 47
7.1 DELAY AND LATENCY MANAGEMENT ......................................................................................................... 47
7.2 DATA OVER-RUN AND UNDER-RUN............................................................................................................. 47
7.3 BUFFER MONITORING .................................................................................................................................. 47
7.4 FRAME CREATION AND DELETION ............................................................................................................... 47
7.5 BUFFER FREEZING (PAUSING) ...................................................................................................................... 48
7.6 VARIABLE BUFFER DEPTH ........................................................................................................................... 48
7.7 SILENCE GENERATION DURING TRANSMIT (PLAYBACK) DATA UNDER-RUN ............................................... 48
7.8 INSERTING SILENCE FRAMES DURING TRUESPEECH PLAYBACK .................................................................. 48
8 TEST MODES................................................................................................................................................... 49
8.1 TEST MODE 1: COUNT MODE ...................................................................................................................... 49
8.2 TEST MODE 2: DIGITAL MILLIWATT............................................................................................................. 49
8.3 TEST MODE 3: INTERNAL LOOPBACK .......................................................................................................... 49
8.4 CODEC LOOPBACK AND MONITORING ....................................................................................................... 49
9 CT8022 HOST CONTROL PROTOCOL ...................................................................................................... 50
9.1 OPERATIONAL MODES ................................................................................................................................. 50
9.2 BASIC PROTOCOL......................................................................................................................................... 51
9.3 RESET & START-UP SEQUENCE.................................................................................................................... 51
Operating Start-up Sequence:.............................................................................................................................. 51
9.4 IDLE ............................................................................................................................................................. 52
9.5 CODEC CONFIGURATION .............................................................................................................................. 52
9.5.1 CODEC Configuration Command....................................................................................................... 52
9.5.2 Sample CODEC Configurations.......................................................................................................... 54
9.6 SETTING THE BASE FRAME SIZE................................................................................................................... 55
9.7 RECORD ....................................................................................................................................................... 57
9.7.1 Transfer Mode..................................................................................................................................... 57
9.7.2 Recording Modes ................................................................................................................................ 59
9.7.3 Peak Level Indication.......................................................................................................................... 60
9.7.4
9.7.5
9.7.6
9.7.7
Record Protocol................................................................................................................................... 60
Select TrueSpeech/G.723.1 Record Rate ............................................................................................ 64
Enable VAD ........................................................................................................................................ 65
Dynamic Switching between TrueSpeech/G.723.1 6.3 and 5.3........................................................... 65
9.7.8 G.723.1 Frame Type Encoding ........................................................................................................... 66
9.7.9 Programming the Record Peak Threshold........................................................................................... 67
9.7.10 Reading the Record Level Value and Threshold Value ...................................................................... 68
9.8 PLAYBACK ................................................................................................................................................... 70
CT8022A11AQC FW Revision 0118
DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
5
All specifications are subject to change without prior notice.
5 Page 
Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
This section contains a list of the CT8022 pins:
Note: The CT8022 is a CMOS device. It is important to make sure that all input pins are connected and
have a valid logic level present at all times. Where noted, certain input pins may require external
pull-up or pull-down resistors.
Signal naming convention: Active low signals are indicated by a trailing “/” or “N” in the signal name as, for
example, SRAMCS/ or SRAMCSN.
Pin Names
HSTDB0
HSTDB1
HSTDB2
HSTDB3
HSTDB4
HSTDB5
HSTDB6
HSTDB7
HSTAB0
HSTAB1
HSTAB2
HSTAB3
HSTRD/
(HSTRDN)
HSTWR/
(HSTWRN)
HSTCS/
(HSTCSN)
TXDREQ
TXDACK/
(TXDACKN)
RXDREQ
RXDACK/
(RXDACKN)
Pin Nrs
103
106
107
108
109
112
113
114
115
116
117
118
122
123
124
127
128
1
2
Type
Function
I/O/Z Host Data Bus. HSTDB0 is the least significant data bit.
I HSTAB0 is the least significant Host Address bit. It selects between the high and low
byte of the Host interface register selected by HSTAB3-1.
I Host Address Bus. These address bits are used to select Host interface register
addressed by Host (in conjunction with HSTCS/).
I Host Read signal. Active Low, output enables HSTDB pins, allowing Host to read from
the selected Host interface register. The interface register is selected via a decode of
HSTAB1-3 if HSTCS/ is active, or the Host Receive Data Buffer access port is
selected directly if RXDACK/ is asserted.
I Host Write signal. Active Low, clocks data from HSTDB pins into selected Host
interface register. The interface register is selected via a decode of HSTAB1-3 if
HSTCS/ is active, or the Host Transmit Data Buffer access port is selected directly if
TXDACK/ is asserted.
I Host Interface Chip Select. Active Low. This signal gates the HSTWR/ and HSTRD/
and HSTAB3-0 address decode during a Host processor access cycle. The
HSTAB3-0 signals should be stable and valid when HSTCS/ is asserted.
This signal must not be asserted during a DMA cycle on the Host port. HSTCS/
must be high when either TXDACK/ or RXDACK/ are asserted (low).
O Active High signal. DMA transmit request. This signal is asserted to indicate that the
device is ready to accept transmit data. Data can be transferred by either DMA or a
Host processor access cycle. The Host can enable or disable this signal via the
Hardware Control Register. By default, this signal is disabled.
I Active Low signal. DMA Transmit Acknowledge. This signal is asserted by an external
DMA controller on the Host port, together with HSTWR/, to clock a byte from the
HSTDB data bus pins into the Host interface Transmit Data Buffer Access port. This
signal provides direct access to the Host Transmit Data Buffer Access Port, without
involving HSTAB0-3 or HSTCS/. If this signal is not used, it should be connected to
VCC via a 10KOhm pull-up resistor. This signal must not be asserted when either
RXDACK/ or HSTCS/ are active.
O Active High signal. DMA receive request. This signal is asserted to indicate that the
device is ready to provide receive data. Data can be transferred by either DMA or a
Host processor access cycle. The Host can enable or disable this signal via the
Hardware Control Register. By default, this signal is disabled.
I Active Low signal. DMA Receive Acknowledge. This signal is asserted by an external
DMA controller on the Host port, together with HSTRD/, to accept a receive data byte
via the HSTDB data bus pins from the Host interface Receive Data Buffer Access port.
This signal provides direct access to the Host Receive Data Buffer Access Port,
without involving HSTAB0-3 or HSTCS/. If this signal is not used, it should be
connected to VCC via a 10KOhm pull-up resistor. This signal must not be asserted
when either TXDACK/ or HSTCS/ are active.
CT8022A11AQC FW Revision 0118
DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CT8022.PDF ] | |
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