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PDF SI5023 Data sheet ( Hoja de datos )
| Número de pieza | SI5023 | |
| Descripción | (SI5022 / SI5023) MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si5022/Si5023
PRELIMINARY DATA SHEET
MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP
Features
High Speed Clock and Data Recovery device with Integrated Limiting Amp:
! Supports OC-48/12/3, STM-16/4/1, ! External Reference Not Required
Gigabit Ethernet, and 2.7 Gbps FEC ! Jitter Generation 3.0 mUIRMS(TYP)
! DSPLL™ Technology
! Loss-of-signal Level Alarm
! Low Power—370 mW (TYP)
! Data Slicing Level Control
! Small Footprint: 5 mm x 5 mm
! Bit-Error-Rate Alarm
! 10 mVPP Differential Sensitivity
! 2.5 V (Si5022) or 3.3 V (Si5023) Supply
Applications
! SONET/SDH/ATM Routers
! Add/Drop Multiplexers
! Digital Cross Connects
! Gigabit Ethernet Interfaces
! SONET/SDH Test Equipment
! Optical Transceiver Modules
! SONET/SDH Regenerators
! Board Level Serial Links
Ordering Information:
See page 14.
Pin Assignments
Si5022/23
Description
The Si5022/23 is a fully integrated, high performance limiting amp and clock and
data recovery (CDR) IC for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1, or
Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided
for OC-48/STM-16 applications that employ forward error correction (FEC). An
external reference clock is not required; applications with or without an external
reference clock are supported. Silicon Laboratories’ DSPLL™ technology
eliminates sensitive noise entry points thus making the PLL less susceptible to
board-level interaction and helping to ensure optimal jitter performance.
The Si5022/23 represents a new standard in low jitter, low power, small size, and
integration for high speed LA/CDRs. It operates from either a 3.3 V (Si5023) or
2.5 V (Si5022) supply over the industrial temperature range (–40°C to 85°C).
Functional Block Diagram
RATESEL0
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
28 27 26 25 24 23 22
1 21 VDD
2 20 REXT
3 19 RESET/CAL
4
GND
Pad
18 VDD
5 17 DOUT+
6 16 DOUT–
7 15 TDI
8 9 10 11 12 13 14
Top View
DSQLCH
D IN +
D IN –
2 Lim iting
AMP
LOS_LVL
Squelch
Control
R etim er
2
BUF
DSPLLTM
Phase-Locked
Loop
2
2
BUF
Control
Bias Gen
DOUT+
DOUT–
CLKDSBL
CLKOUT+
CLKOUT–
LOL
R E S E T /C AL
SLICE_LVL
LTR
R ATS E L [1:0]
LOS
BER_LVL
REFCLK+
REFCLK–
B ER_ALM (Optional)
REXT
Preliminary Rev. 0.46 5/01
Copyright © 2001 by Silicon Laboratories
Si5022/23-DS046
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
1 page  
Si5022/Si5023
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min1 Typ Max1 Unit
Ambient Temperature
Si5022 Supply Voltage2
Si5023 Supply Voltage2
TA
VDD
VDD
–40
2.375
3.135
25
2.5
3.3
85
2.625
3.465
°C
V
V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating
conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless
otherwise stated.
2. The Si5022/23 specifications are guaranteed when using the recommended application circuit (including
component tolerance) of Figure 5 on page 10.
SIGNAL+
SIGNAL–
V
V IS
SIGNAL+
SIGNAL–
A. Operation with Single-Ended Inputs
V
t
0.5 VID
(SIGNAL+) – (SIGNAL–)
V ID
t
B. Operation with Differential Inputs and Outputs
Figure 2. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
Preliminary Rev. 0.46
5
5 Page 
Si5022/Si5023
Functional Description
The Si5022/23 integrates a high-speed limiting amplifier
(LA) with a multi-rate clock and data recovery unit
(CDR) that operates up to 2.7 Gbps. No external
reference clock is required for clock and data recovery.
The limiting amplifier magnifies very low-level input data
signals so that accurate clock and data recovery can be
performed. The CDR uses Silicon Laboratories’ DSPLL
technology to recover a clock synchronous to the input
data stream. The recovered clock is used to retime the
incoming data, and both are output synchronously via
current-mode logic (CML) drivers. Silicon Laboratories’
DSPLL technology ensures superior jitter performance
while eliminating the need for external loop filter
components found in traditional phase-lock loop
implementations.
The limiting amplifier includes a control input for
adjusting the 0/1 data slicing level and provides a loss-
of-signal level alarm output. The CDR includes a bit-
error-rate performance monitor which signals a high bit-
error-rate condition (associated with excessive
incoming jitter) relative to an externally adjustable bit-
error-rate threshold.
The optional reference clock minimizes the CDR
acquisition time and provides a stable reference for
maintaining the output clock when locking to reference
is desired.
Limiting Amplifier
This technology enables clock and data recovery with
far less jitter than is generated using traditional methods
and it eliminates performance degradation caused by
external component aging. In addition, because
external loop filter components are not required,
sensitive noise entry points are eliminated, thus making
the DSPLL less susceptible to board-level noise
sources and making SONET/SDH jitter compliance
easier to attain in the application.
Multi-Rate Operation
The Si5022/23 supports clock and data recovery for
OC-48 and STM-16 data streams. In addition, the PLL
was designed to operate at data rates up to 2.7 Gbps to
support OC-48/STM-16 applications that employ
forward error correction (FEC).
Multi-rate operation is achieved by configuring the
device to divide down the output of the VCO to the
desired data rate. The divide factor is configured by the
RATESEL[0:1] pins. The RATESEL[0:1] configuration
and associated data rates are given in Table 7.
Table 7. Multi-Rate Configuration
RATESEL
[0:1]
SONET/
SDH
Gigabit
Ethernet
OC-48
with
15/14
FEC
CLK
Divider
The limiting amplifier accepts the low-level signal output
from a transimpedance amplifier (TIA). The low-level
signal is amplified to a usable level for the clock and
data recovery unit. The minimum input swing
requirement is specified in Table 2. Larger input
amplitudes (up to the maximum input swing specified in
Table 2) are accommodated without degradation of
performance. The limiting amplifier ensures optimal
data slicing by using a digital dc offset cancellation
technique to remove any dc bias introduced by the
amplification stage.
DSPLL™
The Si5022/23 PLL structure (shown in Figure 1 on
page 4) utilizes Silicon Laboratories' DSPLL technology
to maintain superior jitter performance while eliminating
the need for external loop filter components found in
traditional PLL implementations. This is achieved by
using a digital signal processing (DSP) algorithm to
replace the loop filter commonly found in analog PLL
designs. This algorithm processes the phase detector
error term and generates a digital control value to adjust
the frequency of the voltage controlled oscillator (VCO).
11 2.488 Gbps — 2.67 Gbps 1
10
1.244 Gbps 1.25 Gbps
—
2
01 622.08 Mbps —
—4
00 155.52 Mbps —
— 16
Operation Without an External Reference
The Si5022/23 can perform clock and data recovery
without an external reference clock. Tying the REFCLK
inputs to GND configures the device to operate without
an external reference clock. Clock recovery is achieved
by monitoring the timing quality of the incoming data
relative to the VCO frequency. Lock is maintained by
continuously monitoring the incoming data timing quality
and adjusting the VCO accordingly. Details of the lock
detection and the lock-to-reference functions while in
this mode are described in their respective sections
below.
Note: Without an external reference the acquisition of data is
dependent solely on the data itself and will typically
require more time to acquire lock than when a refer-
ence is applied.
Preliminary Rev. 0.46
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet SI5023.PDF ] | |
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