PDF CY2DP814 Data sheet ( Hoja de datos )

Número de pieza	CY2DP814
Descripción	1:4 Clock Fanout Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! ComLink™ Series CY2DP814 1:4 Clock Fanout Buffer Features • Low voltage operation • VDD = 3.3V • 1:4 fanout • Single-input configurable for LVDS, LVPECL, or LVTTL • Four differential pairs of LVPECL outputs • Drives 50-ohm load • Low input capacitance • Low output skew • Low propagation delay — Typical (tpd < 4 ns) • Industrial versions available • Available packages include TSSOP, SOIC Description The Cypress CY2 series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DP814 fanout buffer features a single LVDS- or a single LVPECL-compatible input and four LVPECL output pairs. Designed for data communications clock management appli- cations, the fanout from a single input reduces loading on the input clock. The CY2DP814 is ideal for both level translations from single-ended to LVPECL and/or for the distribution of LVDS-based clock signals. The Cypress CY2DP814 has configurable input between logic families. The input can be selectable for an LVPECL/LVTTL or LVDS signal, while the output drivers support LVPECL capable of driving 50-ohm lines. Block Diagram Pin Configuration EN1 1 EN2 8 IN+ 6 IN- 7 LVDS / LVPECL / LVTTL CONFIG 2 16 Q1A 15 Q1B 14 Q2A 13 Q2B 12 Q3A 11 Q3B 10 Q4A 9 Q4B OUTPUT LVPECL EN1 CONFIG VDD VDD GND IN+ IN- EN2 1 2 3 4 5 6 7 8 16 Q1A 15 Q1B 14 Q2A 13 Q2B 12 Q3A 11 Q3B 10 Q4A 9 Q4B 16 pin TSSOP / SOIC Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-07060 Rev. B Revised December 15, 2002 1 page ComLink™ Series CY2DP814 VDD VDD - 2V Q Device concept Q User Defined VTT & RTT Figure 1. Differential PECL Output Table 10. High-frequency Parametrics Parameter Fmax Description Maximum Frequency VDD = 3.3V Fmax(20) Maximum Frequency VDD = 3.3V TW Minimum Pulse VDD = 3.3V Conditions 50% Duty Cycle tW(50–50) Standard Load Circuit 20% Duty Cycle tW(20–80) LVPECL Input Vin = VIH(Max.)/VIL(Min.) Vout = VOH(Min.)/VOL (Max.) (Limit) LVPECL Input Vin = VIH(Max.)/VIL(Min.) F = 100 MHz Vout = VOH(Min.)/VOL(Max.).(Limit) Min. Typ. Max. 450 Unit MHz 175 MHz 900 pS P u ls e G enerator A B En1 En2 150 150 GND 10pF Standard Term ination TPA 50 TPC 50 TPB VDD-2V V1A 1 .2 V C M V1B V0Y 1 .2 V C M V0Z T PLH T PHL 1.4 V 0 V D iffe re n tia l 1.0 V 1.4 V 0 V D iffe re n tia l 1.0 V V0Y - V0Z 80% 0 V D iffe re n tia l 20% tt RF Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3, 4, 5, 6, 7] Notes: 3. RL = 50 ohm ± 1%; Zline = 50 ohm 6 = Ó. 4. CL includes instrumentation and fixture capacitance within 6 mm of the UT. 5. TPA and B are used for prop delay and rise/fall measurements. TPC is used for VOC measurements only and otherwise connected to VDD – 2. 6. When measuring Tr/Tf, tpd, VOD point TPC is held at VDD – 2.0V. 7. LVCMOS/LVTTL single-ended input value. Ground either input: when on the B side, non-inversion takes place. If A side is grounded, the signal becomes the complement of the input on B side. See Table 3. Document #: 38-07060 Rev. B Page 5 of 9 5 Page

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