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PDF CY3120 Data sheet ( Hoja de datos )
| Número de pieza | CY3120 | |
| Descripción | CPLD Development Software for PC | |
| Fabricantes | Cypress Semiconductor | |
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t4U.com CY3120®
ee Warp CPLD Development Software for PCFeatures
h• VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364)
Shigh-level language compilers with the following
tafeatures:
a— Designs are portable across multiple devices
.Dand/or EDA environments
— Facilitates the use of industry-standard simulation
wand synthesis tools for board and system-level
w design
w — Support for functions and libraries facilitating
mmodular design methodology
• IEEE Standard 1076 and 1164 VHDL synthesis
osupports:
— Enumerated types
.c— Operator overloading
— For... Generate statements
U— Integers
• IEEE Standard 1364 Verilog synthesis supports:
t4— Reduction and conditional operators
— Blocking and non-blocking procedural assignments
e— While loops
e— Integers
• Several design entry methods support high-level and
hlow-level design descriptions:
— Behavioral VHDL and Verilog (IF...THEN...ELSE;
SCASE...)
— Boolean
ta— Aldec Active-HDL™ FSM graphical Finite State
Machine editor
a— Structural Verilog and VHDL
— Designs can include multiple entry methods (but
.Donly one HDL language) in a single design.
• UltraGen™ Synthesis and Fitting Technology:
— Infers “modules” such as adders, comparators, etc.,
wfrom behavioral descriptions and replaces them with
wcircuits pre-optimized for the target device.
— User selectable speed and/or area optimization on a
block-by-block basis
— Perfect communication between synthesis and
fitting
— Automatic selection of optimal flip-flop type
(D type/T type)
— Automatic pin assignment
• Supports all Cypress Programmable Logic Devices
— PSI™ (Programmable Serial Interface)
— Delta39K™ CPLDs
— Quantum38K™ CPLDs
— Ultra37000™ CPLDs
— FLASH370i™ CPLDs
— MAX340™ CPLDs
— Industry standard PLDs (16V8, 20V8, 22V10)
• VHDL and Verilog timing model output for use with
third-party simulators
• Timing simulation provided by Active-HDL™ Sim
Release 3.3 from Aldec
— Graphical waveform simulator
— Entry and modification of on-screen waveforms
— Ability to probe internal nodes
— Display of inputs, outputs, and high impedance (Z)
signals in different colors
— Automatic clock and pulse creation
— Support for buses
• Architecture Explorer and Dynamic Timing Analysis for
PSI, Delta39K, and Quantum38K devices:
— Graphical representation of exactly how your design
will be implemented on your specific target device
— Zoom from the device level down to the macrocell
level
— Determine the timing for any path and view that path
on a graphical representation of the chip
• Static Timing Report for all devices
• PC Support (Windows 98™, and Windows NT™ 4.0)
• On-line documentation and help
w ww.DataSheet4U.comCypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
wDocument #: 38-03049 Rev. *A
Revised January 9, 2001
1 page  
CY3120
The module portion of a design file is a declaration of what a
design presents to the outside world (the interface). For each
external signal, the module specifies a signal name, a direction
and a data type. In addition, the module declaration specifies
a name by which the entity can be referenced in other
modules. This section shows code segments from four sample
design files. The top portion of each example features the
module declaration.
Behavioral Description
The module portion of a design file specifies the function of the
design. As shown in Figure 1, multiple design-entry methods
are supported in Warp. A behavioral description in Verilog
often includes well known constructs such as If…Else, and
Case statements. Here is a code segment from a simple
state machine design (soda vending machine) that uses
behavioral Verilog to implement the design:
MODULE drink (nickel, dime, quarter, clock,
returnDime, returnNickel,
giveDrink);
INPUT nickel, dime, quarter, clock;
OUTPUT returnDime,returnNickel,giveDrink;
REG returnDime, returnNickel, giveDrink;
PARAMETER zero = 0, five = 1, ten = 2,
fifteen = 3, twenty = 4, twentyfive = 5
owedime = 6;
REG[1:0] drinkStatus;
ALWAYS@ (POSEDGE clock)
BEGIN
giveDrink = 0;
returnDime = 0;
returnNickel = 0;
CASE(drinkStatus)
zero: BEGIN
IF (nickel)
drinkStatus = five;
ELSE IF (dime)
drinkStatus = ten;
ELSE IF (quarter)
drinkStatus = twentyfive;
END
five: BEGIN
IF (nickel)
drinkStatus = ten;
ELSE IF (dime)
drinkStatus = fifteen;
ELSE IF (quarter)
BEGIN
drinkStatus = zero;
giveDrink = 1;
END
END
// Several states are omitted in this
// example. The omitted states are ten
// fifteen, twenty, and twentyfive.
owedime: BEGIN
returnDime = 1;
drinkStatus = zero;
END
default: BEGIN
// This makes sure that the state
// machine resets itself if
// it somehow gets into an undefined state.
drinkStatus = zero;
END
ENDCASE
END
ENDMODULE
Verilog is not a strongly typed language. The simplicity and
readability of the following code is increased by use of the
CASEX. The CASEX command accepts “Don’t Cares” and
chooses the branch depending on the value of the expression.
MODULE sequence (clk, s);
INPUT clk;
INOUT s;
WIRE s;
REG temp;
REG[3:0] count;
ALWAYS@(POSEDGE clk)
CASEX(count)
4’b00XX: BEGIN
temp=1;
count=count+1;
end
4’b01XX: BEGIN
temp=0;
count=count+1;
end
4’b100X: BEGIN
temp=1;
count=count+1;
end
default: BEGIN
temp=0;
count=0;
end
ENDCASE
ASSIGN s=temp;
ENDMODULE
Boolean Equations
A second design-entry method available to Warp Verilog users
is Boolean equations. Figure 4 displays a schematic of a simple
one-bit half adder. The following code describes how this one-bit half
adder can be implemented in Warp with Boolean equations:
x
y
Carry
Sum
Figure 4. One-Bit Half Adder
Document #: 38-03049 Rev. *A
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