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PDF IDT72V70200 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V70200 | |
| Descripción | 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 512 x 512 | |
| Fabricantes | Integrated Device Technology | |
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3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
512 x 512
IDT72V70200
.EATURES:
• 512 x 512 channel non-blocking switching at 2.048 Mb/s
• Per-channel variable or constant throughput delay
• Automatic identification of ST-BUS®/GCI interfaces
• Accept 16 serial data streams of 2.048 Mb/s
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel high impedance output control
• Per-channel Processor Mode
• Control interface compatible to Intel/Motorola CPUs
• Connection memory block programming
• IEEE-1149.1 (JTAG) Test Port
• Available in 84-pin Plastic Leaded Chip Carrier (PLCC),
100-pin Ball Grid Array (BGA), 100-pin Plastic Quad Flatpack
(PQFP) and 100-pin Thin Quad Flatpack (TQFP)
• 3.3V Power Supply
• Operating Temperature Range -40°C to +85°C
DESCRIPTION:
The IDT72V70200 is a non-blocking digital switch that has a capacity of
512 x 512 channels at 2.048 Mb/s. Some of the main features are: program-
mable stream and channel control, Processor Mode, input offset delay and high-
impedance output control.
Per-stream input delay control is provided for managing large multi-chip
switches that transport both voice channel and concatenated data channels. In
addition, input streams can be individually calibrated for input frame offset.
.UNCTIONAL BLOCK DIAGRAM
VCC GND RESET
TMS TDI TDO TCK TRST IC
ODE
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
Receive
Serial Data
Streams
Timing Unit
Test Port
Loopback
Data Memory
Output
MUX
Transmit
Serial Data
Streams
Internal
Registers
Connection
Memory
Microprocessor Interface
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
CLK F0i FE IC
AS/ IM DS/ CS R/W/ A0-A7 DTA D8-D15/ CCO
ALE RD
WR
AD0-AD7
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IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
AUGUST 2001
DSC-5711/3
1 page  
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
.UNCTIONAL DESCRIPTION
The IDT72V70200 is capable of switching 512 x 512, 64 Kbit/s PCM or
N x 64 Kbit/s channel data. The device maintains frame integrity in data
applications and minimum throughput delay for voice applications on a per
channel basis.
The serial input streams of the IDT72V70200 can have a bit rate of
2.048 Mb/s and are arranged in 125µs wide frames, which contain 32 channels
respectively. The data rates on input and output streams are identical.
In Processor Mode, the microprocessor can access input and output time-
slots on a per channel basis allowing for transfer of control and status information.
The IDT72V70200 automatically identifies the polarity of the frame synchroni-
zation input signal and configures the serial streams to either ST-BUS®or GCI
formats.
With the variety of different microprocessor interfaces, IDT72V70200 has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfaces provide compatibility with multiplexed and Motorola non-multiplexed
buses. Thedevicecanalsoresolvedifferentcontrolsignalseliminatingtheuse
of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE).
The frame offset calibration function allows users to measure the frame offset
delay using a frame evaluation pin (FE). The input offset delay can be
programmedforindividualstreamsusinginternalframeinputoffsetregisters,see
Table 8.
The internal loopback allows the TX output data to be looped around to the
RX inputs for diagnostic purposes.
A functional Block Diagram of the IDT72V70200 is shown in Figure 1.
DATA AND CONNECTION MEMORY
The received serial data is converted to parallel format by internal serial-
to-parallel converters and stored sequentially in the data memory. The 8KHz
input frame pulse (F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 512 bytes.
Data to be output on the serial streams (TX0-15) may come from either the
data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
to be output from connection memory, the connection memory control bits must
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
CONNECTION AND PROCESSOR MODES
In the Connection Mode, the addresses of the input source data for all output
channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and
SAB bits), see Table 10. Once the source address bits are programmed by the
microprocessor, the contents of the data memory at the selected address are
transferred to the parallel-to-serial converters and then onto a TX output stream.
By having the each location in the connection memory specify an input
channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.
In Processor Mode, the microprocessor writes data to the connection
memory. Each location in the connection memory corresponds to a particular
output stream and channel number and is transferred directly to the parallel-to-
serial converter one time-slot before it is to be output. This data will be output
ontheTXstreamsineveryframeuntilthedataischangedbythemicroprocessor.
As the IDT72V70200 can be used in a wide variety of applications, the device
also has memory locations to control the outputs based on operating mode.
Specifically, the IDT72V70200 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function. In addition, one of these bits allows the user to control the CCO output.
If an output channel is set to a high-impedance state through the connection
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS®
outputs can be placed in a high impedance state by either pulling the ODE input
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connection memory bits.
The connection memory data can be accessed via the microprocessor
interface. The addressing of the devices internal registers, data and connection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 3 and 5).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For serial
data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz. The
input and output stream data rates will always be identical.
The input 8 KHz frame pulse can be in either ST-BUS® or GCI format. The
IDT72V70200 automatically detects the presence of an input frame pulse and
identifies it as either ST-BUS® or GCI. In ST-BUS® format, every second falling
edge of the master clock marks a bit boundary and the data is clocked in on the
rising edge of CLK, three quarters of the way into the bit cell, see Figure 7. In
GCI format, every second rising edge of the master clock marks the bit boundary
and data is clocked in on the falling edge of CLK at three quarters of the way
into the bit cell, see Figure 8.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streams to be offset with respect to the output stream channel alignment (i.e. F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implementedinlargecentralizedanddistributedswitchingsystems. Because
data is often delayed, this feature is useful in compensating for the skew between
clocks.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR). The maximum allowable skew is +4.5 master
clock (CLK) periods forward with resolution of ½ clock period. The output frame
offset cannot be offset or adjusted. See Figure 5, Table 8 and 9 for delay offset
programming.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V70200 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the IMS register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
5
5 Page 
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 512
COMMERCIALTEMPERATURERANGE
TABLE 7 .RAME ALIGNMENT REGISTER (.AR) BITS
Read/WriteAddress: 02H,
Reset Value:
0000H.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
Bit
15-13
12
11
10-0
Name
Unused
CFE
(Complete Frame Evaluation)
FD11
(Frame Delay Bit 11)
FD10-0
(Frame Delay Bits)
Description
Must be zero for normal operation.
When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment
offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.
The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)
or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
The binary value expressed in these bits refers to the measured input offset value. These bits are rest to
zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
ST-BUS Frame
CLK
Offset Value
FE Input
GCI Frame
CLK
Offset Value
FE Input
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(FD[10:0] = 06H)
(FD11 = 0, sample at CLK LOW phase)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
(FD[10:0] = 09H)
(FD11 = 1, sample at CLK HIGH phase)
Figure 4. Example for Frame Alignment Measurement
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| PDF Descargar | [ Datasheet IDT72V70200.PDF ] | |
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