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PDF COP313CH Data sheet ( Hoja de datos )
| Número de pieza | COP313CH | |
| Descripción | (COPxxxC) Single-Chip CMOS Microcontrollers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 1990
COP413C COP413CH COP313C COP313CH
Single-Chip CMOS Microcontrollers
General Description
The COP413C COP413CH COP313C and COP313CH ful-
ly static single-chip CMOS microcontrollers are members of
the COPSTM family fabricated using double-poly silicon-
gate CMOS technology These controller-oriented proces-
sors are complete microcomputers containing all system
timing internal logic ROM RAM and I O necessary to im-
plement dedicated control functions in a variety of applica-
tions Features include single supply operation with an in-
struction set internal architecture and I O scheme de-
signed to facilitate keyboard input display output and BCD
data manipulation The COP413CH is identical to the
COP413C except for operating voltage and frequency They
are an appropriate choice for use in numerous human inter-
face control environments Standard test procedures and
reliable high-density fabrication techniques provide a cus-
tomized controller-oriented processor at a low end-product
cost
The COP313C COP313CH is the extended temperature
range version of the COP413C COP413CH
For emulation use the ROMless COP404C
Block Diagram
Features
Y Lowest power dissipation (40 mW typical)
Y Low cost
Y Power-saving HALT Mode
Y Powerful instruction set
Y 512 x 8 ROM 32 x 4 RAM
Y 15 I O lines
Y Two-level subroutine stack
Y DC to 4 ms instruction time
Y Single supply operation (3V to 5 5V)
Y General purpose and TRI-STATE outputs
Y Internal binary counter register with MICROWIRETM
compatible serial I O
Y Software hardware compatible with other members of
the COP400 family
Y Extended temperature (b40 C to a85 C) devices
available
FIGURE 1 COP413C 413CH
TRI-STATE is a registered trademark of National Semiconductor Corp
COPSTM MICROWIRETM and STARPLEXTM are trademarks of National Semiconductor Corp
C1995 National Semiconductor Corporation TL DD 8537
TL DD 8537 – 1
RRD-B30M105 Printed in U S A
1 page  
COP313C COP313CH
AC Electrical Characteristics b40 C s TA s a85 C unless otherwise specified
Parameter
Conditions
COP313C
Min Max
COP313CH
Min Max
Units
Instruction Cycle Time
16 DC 4 DC ms
Operating CKI Frequency
d 8 Mode
DC
500
DC
2000
kHz
Instruction Cycle Time
RC Oscillator d 4
R e 30k g5% VCC e 5V
C e 82 pF g 5%
8 16 ms
Instruction Cycle Time
R e 56k g5% VCC e 5V
16
32
16
32 ms
RC Oscillator d 4 (Note 6)
C e 100 pF g 5%
Duty Cycle (Note 5)
Fi e Max Freq Ext Clk
40 60 40 60 %
Rise Time (Note 5)
Fi e Max Freq Ext Clk
60 60 ns
Fall Time (Note 5)
Fi e Max Freq Ext Clk
40 40 ns
Inputs (See Figure 3 )
tSETUP
tHOLD
G Inputs
SI Input
L Inputs
tc 4 a 2 8
12
68
10
tc 4 a 0 7
03
17
0 25
ms
ms
ms
ms
Output Propagation
Delay
tPD1 tPD0
VOUT e 1 5V CL e 100 pF
RL e 5k
40
1 0 ms
Note 1 Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI CKO open and all other pins pulled up to VCC with 5k
resistors See current drain equation on page 13
Note 2 The Halt mode will stop CKI from oscillating
Note 3 SO output sink current must be limited to keep VOL less than 0 2 VCC when part is running in order to prevent entering test mode
Note 4 Voltage change must be less than 0 5V in a 1 ms period
Note 5 This parameter is only sampled and not 100% tested
Note 6 Variation due to the device included
Connection Diagram
DIP
Top View
TL DD 8537 – 2
Pin Descriptions
Pin
L7 – L0
G3 – G0
SI
SO
SK
CKI
CKO
RESET
VCC
GND
Description
8-bit bidirectional I O port with TRI-STATE
4-bit bidirectional I O port
Serial input (or counter input)
Serial output (or general purpose output)
Logic-controlled clock
(or general purpose output)
System oscillator input
Crystal oscillator output or NC
System reset input
System power supply
System Ground
FIGURE 2
Order Number COP313C-XXX D COP313CH-XXX D
COP413C-XXX D or COP413CH-XXX D
See NS Hermetic Package Number D20A
Order Number COP313C-XXX N COP313CH-XXX N
COP413C-XXX N or COP413CH-XXX N
See NS Molded Package Number N20A
Order Number COP313C-XXX WM or
COP413C-XXX WM
See NS Small Outline Package Number M20B
5
5 Page 
COP413C Instruction Set
Table II is a symbol table providing internal architecture in-
struction operand and operational symbols used in the in-
struction set table
Table III provides the mnemonic operand machine code
data flow skip conditions and description associated with
each instruction in the COP413C instruction set
TABLE II COP413C Instruction Set Table Symbols
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
A 4-bit Accumulator
B 6-bit RAM Address Register
Br Upper 2 bits of B (register address)
Bd Lower 4 bits of B (digit address)
C 1-bit Carry Register
EN 4-bit Enable Register
G 4-bit Register to latch data for G I O Port
L 8-bit TRI-STATE I O Port
M 4-bit contents of RAM Memory pointed to by B
Register
PC 9-bit ROM Address Register (program counter)
Q 8-bit Register to latch data for L I O Port
SA 9-bit Subroutine Save Register A
SB 9-bit Subroutine Save Register B
SIO 4-bit Shift Register and Counter
SK Logic-Controlled Clock Output
Symbol
Definition
INSTRUCTION OPERAND SYMBOLS
d 4-bit Operand Field 0 – 15 binary (RAM Digit Select)
r 2-bit Operand Field 0 – 3 binary (RAM Register
Select)
a 9-bit Operand Field 0 – 511 binary (ROM Address)
y 4-bit Operand Field 0 – 15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
a Plus
b Minus
x Replaces
Is exchanged with
e Is equal to
A The one’s complement of A
Z Exclusive-OR
Range of values
TABLE III COP413C Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
0011 0000
xA a C a RAM(B) A Carry
Carry x C
Add with Carry Skip on
Carry
ADD
x31 0011 0001 A a RAM(B) A
None
Add RAM to A
AISC
xy
5b 0101 y
Aay A
Carry
Add immediate Skip on
Carry (y i 0)
CLRA
x00 0000 0000 0 A
None
Clear A
COMP
x40 0100 0000 A A
None
One’s complement of A to A
NOP
44 0100 0100 None
None
No Operation
xRC
32 0011 0010 ‘‘0’’ C
None
Reset C
xSC
22 0010 0010 ‘‘1’’ C
None
Set C
XOR
x02 0000 0010 A Z RAM(B) A
None
Exclusive-OR RAM with A
11
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| PDF Descargar | [ Datasheet COP313CH.PDF ] | |
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