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Número de pieza | M6MGT33BS8BWG-P | |
Descripción | CMOS SRAM | |
Fabricantes | Renesas | |
Logotipo | ||
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Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
Renesas LSIs
M6MGB/T33BS8BWG-P
33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS FLASH MEMORY &
8,388,608-BIT (524,288-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
Description
The M6MGB/T33BS8BWG-P is a Stacked Chip Scale
Package (S-CSP) that contents 32M-bit Flash memory and
8M-bit SRAM in a 66-pin Stacked CSP with leaded solder
ball.
The M6MGB/T33BS8BWG-P is suitable for a high
performance cellular phone and a mobile PC that are
required to be small mounting area, weight and small power
dissipation.
32M-bit Flash memory is a 2,097,152 words, single power
supply and high performance non-volatile memory fabricated
by CMOS technology for the peripheral circuit and DINOR
(Divided bit-line NOR) architecture for the memory cell. All
memory blocks are locked and can not be programmed or
erased, when F-WP# is Low. Using Software Lock Release
function, program or erase operation can be executed.
Features
Access Time Flash
SRAM
Supply Voltage
Ambient Temperature
Package
8M-bit SRAM is a 524,288 words asynchronous SRAM
fabricated by CMOS technology.
Application
Mobile communication products
70ns (Max.)
85ns (Max.)
F-VCC =VCC=2.7 ~ 3.0V
Ta=-40 ~ 85 °C
66 pin S-CSP
Ball pitch 0.80mm
Outer-ball: Sn - Pb
PIN CONFIGURATION (TOP VIEW)
INDEX(Laser Marking)
F-VCC
S-VCC
F-GND
S-GND
A0-A18
F-A19-F-A20
DQ0-DQ15
F-CE#
S-CE1#
S-CE2
A NC
NC
B NC
NC
www.DataSheet4U.comC NC A18 S-LB# F-WP# S-GND F-WE# A16 F-A20
D A5 A17 S-UB# NC F-RP# F-RY/BY# A8 A11
E A4 A7 S-OE# F-A19
A10 A15
F A0 A6
DQ11
A9 A14
G F-CE# A3 DQ9
DQ12 DQ13 DQ15 A13
H F-GND A2 DQ8 DQ10 S-CE2 DQ6 S-WE# A12
J F-OE# A1 DQ0 DQ2 S-VCC DQ4 DQ14 F-GND
K NC S-CE1# DQ1 DQ3 F-VCC DQ5 DQ7 NC
L NC
NC
M NC
NC
12 34 56 7 8
8.0 mm
NC:Non Connection
: VCC for Flash Memory
: VCC for SRAM
: GND for Flash Memory
: GND for SRAM
: Common address for Flash/SRAM
: Address for Flash
: Data I/O
: Flash chip enable
: SRAM chip enable1
: SRAM chip enable2
F-OE#
S-OE#
F-WE#
S-WE#
F-WP#
F-RP#
F-RY/BY#
S-LB#
S-UB#
:Output enable for Flash
:Output enable for SRAM
:Write enable for Flash
:Write enable for SRAM
:Write protect for Flash
:Reset power down for Flash
:Flash Ready/Busy
:Lower byte control for SRAM
:Upper byte control for SRAM
1 Rev.0.1_48a_bebz
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