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PDF ICS9169C-27 Data sheet ( Hoja de datos )
| Número de pieza | ICS9169C-27 | |
| Descripción | Frequency Generator for Pentium Based Systems | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS9169C-27
Frequency Generator for Pentium Based Systems
General Description
Features
The ICS9169C-27 is a low-cost frequency generator
designed specifically for Pentium based chip set systems.
The integrated buffer minimizes skew and provides all the
clocks required. A 14.318 MHz XTAL oscillator provides
the reference clock to generate standard Pentium
frequencies. The CPU clock makes gradual frequency
transitions without violating the PLL timing of internal
microprocessor clock multipliers.
Twelve CPU clock outputs provide sufficient clocks for the
CPU, chip set, memory and up to two DIMM connectors (with
four clocks to each DIMM). Either synchronous(CPU/2) or
asynchronous (32 MHz) PCI bus operation can be selected
by latching data on the BSEL input
Block Diagram
Twelve selectable CPU clocks operate up to 83.3MHz
Maximum CPU jitter of ± 200ps
Six BUS clocks support sync or async bus operation
250ps skew window for CPU outputs, 500ps skew
window for BUS outputs
CPU clocks BUS clocks skew 1-4ns (CPU early)
Integrated buffer outputs drive up to 30pF loads
3.0V - 3.7V supply range, CPU(1:6) outputs 2.5V(2.375-
2.62V) VDD option
32-pin SOIC/SOJ package
Logic inputs latched at Power-On for frequency selection
saving pins as Input/Output
48 MHz clock for USB support and 24 MHz clock for FD.
Pin Configuration
DataSheet4U.com
DataShee
VDD Groups:
VDD = X1, X2, REF/BSEL
VDDC1 = CPU1-6
VDDC2 = CPU7-12 & PLL Core
VDDB = BUS1-6
VDDF = 48/24 MHz
Latched Inputs:
L1 = BSEL
L2 = FS0
L3 = FS1
DataSheet4UL.4c=omFS2
9169C-27 Rev C 04/16/98
32-Pin SOIC/SOJ
ADDRESS
SELECT
FS2 FS1 FS0
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
CPU(1:12)
(MHz)
50
60
66.6
REF/2
55
75
83.3
Tristate
Functionality
3.3V±10%, 0-70°C
Crystal (X1, X2) = 14.31818 MHz
BUS (1:6)MHz
48MHz 24MHz
BSEL=1 BSEL=0
REF
25 32
30 32
33.3 32
48 24 REF
48 24 REF
48 24 REF
REF/4 REF/3 REF/2 REF/4 REF
27.5 32
48 24 REF
37.5
41.7
Tristate
32
32
Tristate
48 24 REF
48 24 REF
Tristate Tristate Tristate
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
1 page  
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ICS9169C-27
Technical Pin Function Descriptions
et4U.com
VDD
This is the power supply to the internal logic of the device as
well as the following clock output buffers:
clocks is control-led by the supply that is applied to the
VDD pin of the device. See the Functionality table at the
beginning of this data sheet for a list of the specific
A. REF clock output buffers
B. BUS clock output buffers
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
C. Fixed clock output buffers
FS0, FS1, FS2
This pin may be operated at any voltage between 3.0 and 5.5
volts. Clocks from the listed buffers that it supplies will
have a voltage swing from ground to this level. For the
actual guaranteed high and low voltage levels of these
clocks, please consult the AC parameter table in this data
sheet.
These pins control the frequency of the clocks at the CPU,
CPUL, BUS & SDRAM pins. See the Funtionality table at
the beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies. The
device reads these pins at power-up and stores the
programmed selection code in an internal data latch. (See
GND
This is the power supply ground return pin for the internal
programming section of this data sheet for configuration
circuitry recommendations.
logic of the device as well as the following clock output
buffers:
BSEL
This pin controls whether the BUS clocks will be synchronous
A. REF clock output buffers
B. BUS clock output buffers
C. CPU clock output buffers
D. Fixed clock output buffers
(run at half the frequency) with the CPU and CPUL clocks or
whether they will be asynchronous (run at a pre-programmed
fixed frequency) clock rate. It is a shared pin and is pro
DataSheet4Ugr.acmommed the same way as the frequency select pins.
X1
This pin serves one of two functions. When the device is
used with a crystal, X1 acts as the input pin for the reference
signal that comes from the discrete crystal. When the device
is driven by an external clock signal, X1 is the device input
pin for that reference clock. This pin also implements an
internal crystal loading capacitor that is connected to ground.
See the data tables for the value of the capacitor.
VDDC (1:2)
These are the power supply pins for the CPU (1:6) and CPU
(7:12) clock buffers. By separating the clock power pins,
each group can receive the appropriate power decoupling
and bypassing necessary to minimize EMI and crosstalk
between the individual signals. VDDC1 can be reduced to
2.5V VDD for advanced processor clocks, which will bring
CPU (1:6) outputs at 0 to 2.5V output swings.
X2
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is
48 MHz
This is a fixed frequency clock that is typically used to drive
Super I/O peripheral device needs.
an output signal that drives (or excites) the discrete crystal.
This pin also implements an internal crystal loading capacitor
that is connected to ground. See the data tables for the value
of the capacitor.
24 MHz
This is a fixed frequency clock that is typically used to drive
Keyboard controller clock needs.
CPU
This pin is the clock output that drives processor and other
CPU related circuitry that require clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of
these clocks is controlled by that which is applied to the
REF
This is a fixed frequency clock that runs at the same frequency
as the input reference clock (typically 14.31818 MHz) is
and typically used to drive Video and ISA BUS
requirements.
VDDC pins of the device. See note on VDDC (1:2). See the
Functionality table at the beginning of this data sheet for a
list of the specific frequencies that this clock operates at and
VDDB
This power pin supplies the BUS clock buffers.
the selection codes that are necessary to produce these
frequencies.
VDDF
This power pin supplies the 48/24 MHz clocks.
DataShee
BUS
This pin is the clock output that is intended to drive the
systems plug-in card bus. The voltage swing of these
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