PDF CY7C1513V18 Data sheet ( Hoja de datos )

Número de pieza	CY7C1513V18
Descripción	(CY7C15xxV18) SRAM 4-Word Burst Architecture
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com PRELIMINARY CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 72-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) accounts for clock skew and flight time mismatching • Echo clocks (CQ and CQ) simplify data capture in high speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Available in ×8,x9, ×18, and ×36 configurations • Full data coherency providing most current data • Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd) • 15 × 17 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 × 15 matrix) • Variable drive HSTL output buffers • JTAG 1149.1 Compatible test access port • Delay Lock Loop (DLL) for accurate data placement Configurations CY7C1511V18–8M x 8 CY7C1526V18–8M x 9 CY7C1513V18–4M x 18 CY7C1515V18–2M x 36 The CY7C1511V18, CY7C1526V18, CY7C1513V18, and CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1511V18) or 9-bit words (CY7C1526V18) or 18-bit words (CY7C1513V18) or 36-bit words (CY7C1515V18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simpli- fying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05363 Rev. A Revised August 11, 2004 DataSheet4 U .com 1 page www.DataSheet4U.com PRELIMINARY Pin Configurations (continued) CY7C1513V18 (4M × 18)–15 × 17 FBGA 1 2 3 4 56 7 8 A CQ VSS/144M A WPS BWS1 K NC/288M RPS B NC Q9 D9 A NC K BWS0 A C NC NC D10 VSS A NC A VSS D NC D11 Q10 VSS VSS VSS VSS VSS E NC NC Q11 VDDQ VSS VSS VSS VDDQ F NC Q12 D12 VDDQ VDD VSS VDD VDDQ G NC D13 Q13 VDDQ VDD VSS VDD VDDQ H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ J NC NC D14 VDDQ VDD VSS VDD VDDQ K NC NC Q14 VDDQ VDD VSS VDD VDDQ L NC Q15 D15 VDDQ VSS VSS VSS VDDQ M NC NC D16 VSS VSS VSS VSS VSS N NC D17 Q16 VSS A A A VSS P NC NC Q17 A ACAA R TDO TCK A A A C A A CY7C1515AV18 (2M × 36)–15 × 17FBGA CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/288M A WPS BWS2 K BWS1 RPS A VSS/144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 N D34 D26 Q25 VSS A A A VSS Q10 D9 D2 D1 P Q35 D35 Q26 A A C A A Q9 D0 Q0 R TDO TCK A A ACAA A TMS TDI Document #: 38-05363 Rev. A DataSheet4 U .com Page 5 of 23 5 Page www.DataSheet4U.com PRELIMINARY CY7C1511V18 CY7C1526V18 CY7C1513V18 CY7C1515V18 Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied .... –10°C to +85°C Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V DC Applied to Outputs in High-Z .........–0.5V to VDDQ + 0.3V DC Input Voltage[14] ............................ –0.5V to VDDQ + 0.3V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V Latch-up Current..................................................... >200 mA Operating Range Range Com’l Ambient Temperature (TA) 0°C to +70°C VDD[15] 1.8 ± 0.1V VDDQ[15] 1.4V to VDD DC Electrical Characteristics Over the Operating Range[11] Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD ISB1 Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[14] Input LOW Voltage[14] Input Load Current Output Leakage Current Input Reference Voltage[16] VDD Operating Supply Automatic Power-down Current Test Conditions [12] [13] IOH = −0.1 mA, Nominal Impedance IOL = 0.1mA, Nominal Impedance GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled Typical Value = 0.75V VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 167 MHz 200 MHz 250 MHz Max. VDD, Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC, Inputs Static 167 MHz 200 MHz 250 MHz Min. 1.7 1.4 VDDQ/2-0.12 VDDQ/2 -0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.3 −5 −5 0.68 Typ. 1.8 1.5 0.75 Notes: 11. All Voltage referenced to Ground. 12. Output are impedance controlled. Ioh=−(Vddq/2)/(RQ/5) for values of 175ohms <= RQ <= 350ohms. 13. Output are impedance controlled. Iol=(Vddq/2)/(RQ/5) for values of 175ohms <= RQ <= 350ohms. 14. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2). 15. Power-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD 16. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller. Max. 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ+0.3 VREF–0.1 5 5 0.95 TBD TBD TBD TBD TBD TBD Unit V V V V V V V V µA µA V mA mA mA mA mA mA Document #: 38-05363 Rev. *A DataSheet4 U .com Page 11 of 23 11 Page

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