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PDF HT47C20-1 Data sheet ( Hoja de datos )
| Número de pieza | HT47C20-1 | |
| Descripción | R-F Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT47R20A-1/HT47C20-1
R-F Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0029E Using the Time Base Function in the HT47R20A-1
- HA0030E Using the RTC in the HT47R20A-1
- HA0034E Using the Buzzer Function in the HT47R20A-1
- HA0036E Using the PFD Function in the HT47R20A-1
- HA0045E Distinguishing between the Different Devices in the HT47 MCU Series
Features
· Operating voltage: 2.2V~5.5V
· Eight bidirectional I/O lines
· Four input lines
· One interrupt input
· One 16-bit programmable timer/event counter with
PFD (programmable frequency divider) function
· On-chip crystal and RC oscillator for system clock
· One 32.768kHz crystal oscillator for real time clock or
system clock
· Watchdog Timer
· 2K´16 program memory
· 64´8 data memory RAM
· One Real Time Clock (RTC)
· One 8-bit prescaler for RTC
· One low voltage detector
· One low voltage reset circuit
· One buzzer output
· HALT function and wake-up feature reduce power
consumption
· LCD bias C type or R type
· One LCD driver with 20´2, 20´3 or 19´4 segments
· One IR carrier output
· Two channels RC type A/D converter
· Four-level subroutine nesting
· Bit manipulation instruction
· 16-bit table read instruction
· Up to 1ms instruction cycle with 4MHz system clock
· All instructions in one or two machine cycles
· 63 powerful instructions
· 64-pin QFP package
General Description
The HT47R20A-1/HT47C20-1 are 8-bit, high perfor-
mance, RISC architecture microcontroller devices spe-
cifically designed for applications that interface directly
to analog signals, such as those from sensors. The
mask version HT47C20-1 is fully pin and functionally
compatible with the OTP version HT47R20A-1 device.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, 2-channel RC type A/D Converter,
LCD driver, HALT and wake-up functions, enhance the
versatility of these devices to suit a wide range of Resis-
tor to Frequency application possibilities such as sensor
signal processing, remote metering, industrial control,
consumer products, subsystem controllers, etc.
Rev. 1.70
1 June 14, 2005
1 page  
HT47R20A-1/HT47C20-1
Symbol
Parameter
ISTB5
Standby Current
(*fS=32.768kHz OSC)
Test Conditions
VDD Conditions
3V No load, system HALT,
LCD on at HALT, R type,
5V 1/3 bias
Min.
¾
¾
Typ. Max. Unit
13 25 mA
28 50 mA
ISTB6
Standby Current
(*fS=WDT RC OSC)
3V No load, system HALT,
¾ 14 25 mA
LCD on at HALT, R type,
5V 1/2 bias
¾ 26 50 mA
ISTB7
Standby Current
(*fS=WDT RC OSC)
3V No load, system HALT,
¾ 10 20 mA
LCD on at HALT, R type,
5V 1/3 bias
¾ 19 40 mA
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0 ¾ 0.3VDD V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
3V
5V
0.7VDD ¾
VDD
V
¾
0.7VDD ¾
VDD
V
VIL2 Input Low Voltage (RES)
¾
¾
0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES)
¾
¾
0.9VDD ¾
VDD
V
IOL1 I/O Port Sink Current
3V
VOL=0.1VDD
5V
6 12 ¾ mA
10 25 ¾ mA
IOH1 I/O Port Source Current
3V
VOH=0.9VDD
5V
-2 -4 ¾ mA
-5 -8 ¾ mA
IOL2
LCD Common and Segment
Current
3V
VOL=0.1VDD
5V
210 420
350 700
¾
¾
mA
mA
IOH2
LCD Common and Segment
Current
3V
VOH=0.9VDD
5V
-80
-180
-160
-360
¾
¾
mA
mA
IOL3 RC Oscillation Output Sink Current 3V VOL=0.3V
5 10 ¾ mA
IOH3
RC Oscillation Output Source
Current
3V VOH=2.7V
-5 -10 ¾ mA
RPH
Pull-high Resistance of I/O Ports
and INT0, INT1
3V
5V
¾
20 60 100 kW
10 30 50 kW
VLVR
VLVD
Low Voltage Reset
Low Voltage Detector Voltage
¾
¾
¾
2.5 3.2 3.6
3.0 3.3 3.6
V
V
Note: ²*² tSYS= 1/fSYS
²**² for power on protection
Rev. 1.70
5 June 14, 2005
5 Page 
HT47R20A-1/HT47C20-1
Bit No.
0
1
2
3
4
5
6
7
Label
EMI
EEI
ETBI
ERTI
EIF
TBF
RTF
¾
Function
Control the master (global) interrupt (1= enabled; 0= disabled)
Control the external interrupt (1= enabled; 0= disabled)
Control the time base interrupt (1= enabled; 0= disabled)
Control the real time clock interrupt (1= enabled; 0= disabled)
External interrupt request flag (1= active; 0= inactive)
Time base request flag (1= active; 0= inactive)
Real time clock request flag (1= active; 0= inactive)
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
0
1~3
4
5~7
Label
ETI
¾
TF
¾
Function
Control the timer/event counter interrupt (1= enabled; 0=disabled)
Unused bit, read as ²0²
Internal timer/event counter request flag (1= active; 0= inactive)
Unused bit, read as ²0²
INTC1 (1EH) Register
Once an interrupt subroutine is serviced, all other inter-
rupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting.
Other interrupt requests may happen during this inter-
val, but only the interrupt request flag is recorded. If a
certain interrupt needs servicing within the service rou-
tine, the EMI bit and the corresponding bit of INTC0 or
INTC1 may be set allow interrupt nesting. If the stack is
full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the SP is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
All these kinds of interrupt have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then by
branching to subroutines at specified location(s) in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and status
register (STATUS) is altered by the interrupt service
program which corrupts the desired control sequence,
the contents must be saved first.
External interrupt is triggered by a high to low transition
of INT and the related interrupt request flag (EIF; bit 4 of
INTC0) will be set. When the interrupt is enabled, and
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The internal timer/event counter interrupt is initialized
by setting the timer/event counter interrupt request flag
(TF; bit 4 of INTC1), caused by a timer A or timer B over-
flow. When the interrupt is enabled, and the stack is not
full and the TF bit is set, a subroutine call to location 10H
will occur. The related interrupt request flag (TF) will be
reset and the EMI bit cleared to disable further inter-
rupts.
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC0), caused
by a regular time base signal. When the interrupt is en-
abled, and the stack is not full and the TBF bit is set, a
subroutine call to location 08H will occur. The related in-
terrupt request flag (TBF) will be reset and the EMI bit
cleared to disable further interrupts.
The real time clock interrupt is initialized by setting the
real time clock interrupt request flag (RTF; bit 6 of
INTC0), caused by a regular real time clock signal.
When the interrupt is enabled, and the stack is not full
and the RTF bit is set, a subroutine call to location 0CH
will occur. The related interrupt request flag (RTF) will be
reset and the EMI bit cleared to disable further inter-
rupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI instruc-
tion is executed or the EMI bit and the related interrupt
control bit are set to 1 (if the stack is not full). To return
from the interrupt subroutine, RET or RETI instruction
may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Rev. 1.70
11 June 14, 2005
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT47C20-1.PDF ] | |
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