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ADUC7033 PDF даташит

Спецификация ADUC7033 изготовлена ​​​​«Analog Devices» и имеет функцию, называемую «(ADUC7030 / ADUC7033) Integrated Precision Battery Sensor».

Детали детали

Номер произв ADUC7033
Описание (ADUC7030 / ADUC7033) Integrated Precision Battery Sensor
Производители Analog Devices
логотип Analog Devices логотип 

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ADUC7033 Даташит, Описание, Даташиты
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Preliminary Technical Data
Integrated Precision Battery Sensor
For Automotive
ADuC7030/ADuC7033
FEATURES
High precision ADCs
Dual channel, simultaneous sampling, 16-bit Σ∆ ADCs
Programmable ADC throughput from 1 Hz to 8 kHz
On-chip 5ppm/°C voltage reference
Current channel
Fully differential, buffered Input
Programmable gain from 1 to 512
ADC input range: −200 mV to +300 mV
Digital comparators, with current accumulator feature
Voltage channel
Buffered, on-chip attenuator for 12V battery inputs
Temperature channel
External and on-chip temperature sensor options
Microcontroller
ARM7TDMI core, 16-/32-bit RISC architecture
20.48 MHz PLL with programmable divider
PLL Input Source
On-chip precision oscillator
On-chip low-power oscillator
External (32.768 kHz) watch crystal
JTAG port supports code download and debug
Memory
32 kbytes Flash/EE memory, 4 kbytes SRAM (ADuC7030)
96 kbytes Flash/EE memory, 6 kbytes SRAM (ADuC7033)
10 kcycles Flash/EE endurance, 20 years Flash/EE retention
In-circuit download via JTAG and LIN
On-chip peripherals
LIN 2.0 (slave) compatible support via UART with
hardware synchronization
Flexible wake-up I/O pin, master/slave SPI serial I/O
9-pin GPIO port, 3 X general purpose timers
Wake-up and watchdog timers
Power supply monitor, on-chip power-on-reset
Power
Operates directly from 12 V battery supply
Current consumption
Normal mode 10 mA at 10 MHz
Low power monitor mode
Packages and temperature range
48 Pin LFCSP 7X7 mm or 48 Pin LQFP 7X7 mm body
package
Fully specified for −40°C to +115°C operation
APPLICATIONS
Battery sensing/management for automotive systems
FUNCTIONAL BLOCK DIAGRAM
TCK TDI TDO NTRST TMS
IIN+
IIN–
VBAT
PRECISION ANALOG ACQUISITION
PGA
16-BIT
Σ-ADC
ADuC7030/ADuC7033
2.6V LDO
PSM
POR
MEMORY
32KB FLASH
4KB RAM
RESET
VTEMP
GND_SW
VREF
RESULT
DIGITAL
ACCUMULATOR COMPARATOR
MUX BUF
16-BIT
Σ-ADC
TEMPERATURE PRECISION
SENSOR
REFERENCE
ARM7TDMI
MCU
20MHz
PRECISION
OSC
LOW POWER
OSC
ON-CHIP PLL
XTAL1
XTAL2
3 × TIMERS
WDT
W/U TIMER
GPIO PORT
UART PORT
SPI PORT
LIN
WU
STI
LIN/BSD
Figure 1.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices.Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.









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ADUC7033 Даташит, Описание, Даташиты
ADuC7030/ADuC7033
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
ADuC7030 Flash/EE Memory ............................................. 27
Applications....................................................................................... 1
ADuC7033 Flash/EE Memory ............................................. 27
Functional Block Diagram .............................................................. 1
ADuC7030 Flash/EE Control Interface .................................. 27
Specifications..................................................................................... 6
FEE0CON Register: ............................................................... 28
Electrical Specifications............................................................... 6
Command Sequence for Executing a Mass Erase.............. 29
Timing Specifications ................................................................ 12
FEE0STA Register: ................................................................. 29
SPI Timing Specifications ..................................................... 12
FEE0MOD Register: .............................................................. 30
LIN Timing Specifications .................................................... 16
FEE0ADR Registers: .............................................................. 30
Terminology .................................................................................... 17
FEE0DAT Registers................................................................ 30
Absolute Maximum Ratings.......................................................... 18
ADuC7030 Flash/EE memory security................................... 31
ESD Caution................................................................................ 18
Flash/EE Memory Protection Registers: ............................. 31
Pin Configuration and Function Descriptions........................... 19
Theory of Operation ...................................................................... 22
Overview of the ARM7TDMI core.......................................... 22
Thumb Mode (T) ................................................................... 22
Multiplier (M)......................................................................... 22
EmbeddedICE (I) ................................................................... 22
ARM7 Exceptions .................................................................. 23
ARM Registers ........................................................................ 23
Interrupt Latency.................................................................... 23
Memory Organisation ............................................................... 24
Memory Format ..................................................................... 24
SRAM....................................................................................... 24
Remap ...................................................................................... 24
Sequence to Write the Key and Set Permanent Protection
.................................................................................................. 32
ADuC7033 Flash/EE Control Interface .................................. 32
FEE0CON and FEE1CON Registers: .................................. 33
Command Sequence for executing a Mass Erase .............. 34
FEE0STA and FEE1STA Registers: ...................................... 34
FEE0ADR and FEE1ADR Registers: ................................... 35
FEE0DAT and FEE1DAT Registers: .................................... 35
FEE0MOD and FEE1MOD Registers: ................................ 35
ADuC7033 Flash/EE Memory Security .................................. 36
Block0, Flash/EE Memory Protection Registers: ............... 36
Block1, Flash/EE Memory Protection Registers: ............... 37
Sequence to Write the Key and Set Permanent Protection:
.................................................................................................. 38
Remap Operation ................................................................... 25
Flash/EE Memory Reliability.................................................... 38
SYSMAP0 Register:................................................................ 25
CODE Execution time from SRAM and Flash/EE ................ 39
ADuC7030/ADuC7033 Reset................................................... 26
Execution from SRAM .......................................................... 39
RSTSTA Register: ................................................................... 26
Execution from Flash/EE ...................................................... 39
RSTCLR Register:................................................................... 26
ADuC7030/ADuC7033 Kernel ................................................ 40
Flash/EE Memory and the ADuC7030/ADuC7033 .............. 27
Memory Mapped Registers ....................................................... 42
(1) Serial Downloading (In-Circuit Programming).......... 27
16-Bit Σ−∆ Analog to Digital Converters ............................... 48
(2) JTAG access....................................................................... 27
Current Channel ADC (I-ADC).......................................... 48
Rev. PrE | Page 2 of 150









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ADUC7033 Даташит, Описание, Даташиты
Preliminary Technical Data
ADuC7030/ADuC7033
Voltage/Temperature Channel ADC (V/T-ADC) ..................50
ADC Sinc3 Digital Filter Response ......................................67
ADC Ground Switch ..................................................................51
ADC Noise Performance Tables ...............................................52
ADC Calibration.....................................................................69
Using the Offset and Gain Calibration ................................70
ADC MMR Interface..................................................................53
Understanding the Offset and Gain Calibration Registers70
ADC Status Register: ..............................................................53
ADC Interrupt Mask Register:..............................................55
ADC Diagnostics ........................................................................71
Current ADC Diagnostics .....................................................71
ADC Mode Register: ..............................................................55
Voltage/Temperature ADC Diagnostics ..............................71
Current Channel ADC Control Register:............................57
Voltage/Temperature Channel ADC Control Register:.....58
Power Supply Support Circuits .....................................................72
ADuC7030/ADuC7033 System Clocks........................................73
ADC Filter Register: ...............................................................59
PLLSTA Register: ....................................................................74
ADC Configuration Register: ...............................................61
PLLCON Pre-write Key PLLKEY0:......................................75
Current Channel ADC Data Register: .................................62
Voltage Channel Data Register: ............................................62
PLLCON Pre-write Key PLLKEY1:......................................75
PLLCON Register: ..................................................................75
Temperature Channel ADC Data Register:.........................62
Current Channel ADC Offset Calibration Register:..........62
Voltage Channel Offset Calibration Register: .....................63
POWCON Pre-write Key POWKEY0: ................................75
POWCON Pre-write Key POWKEY1: ................................75
POWCON Register: ...............................................................76
Temperature Channel Offset Calibration Register:............63
ADuC7030/ ADuC7033 Low Power Clock Calibration........77
Current Channel ADC Gain Calibration Register: ............63
Voltage Channel Gain Calibration Register: .......................64
OSC0TRM Register:...............................................................78
OSC0CON Register:...............................................................78
Temperature Channel Gain Calibration Register:..............64
OSC0STA Register:.................................................................79
Current Channel ADC Result Counter Limit Register: ....64
Current Channel ADC Result Count Register:...................64
OSC0VAL0 Register: ..............................................................79
OSC0VAL1 Register: ..............................................................79
Current Channel ADC Threshold Register:........................65
Processor Reference Peripherals ...................................................80
Current Channel ADC Threshold Count Limit Register:.65
Current Channel ADC Threshold Count Register: ...........65
Interrupt System..........................................................................80
IRQ............................................................................................81
Current Channel ADC Accumulator Register:...................65
FIQ ............................................................................................81
Low Power Voltage Reference Scaling Factor .....................66
ADC Power Modes of Operation..............................................66
Timers ............................................................................................... 82
Timer0—Life-Time timer ..........................................................83
ADC Startup Procedure .........................................................66
Timer0 Value Register:...........................................................83
ADC Normal Power Mode ....................................................66
Timer0 Capture Register: ......................................................83
ADC Low Power Mode ..........................................................66
ADC Low Power-Plus Mode .................................................67
Timer0 Control Register:.......................................................84
Timer0 Load Registers: ..........................................................85
ADC comparator and accumulator......................................67
Timer0 Clear Register: ...........................................................85
Rev. PrE| Page 3 of 150










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