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PDF CY2PD817 Data sheet ( Hoja de datos )
| Número de pieza | CY2PD817 | |
| Descripción | PECL/CMOS Buffer | |
| Fabricantes | Cypress Semiconductor | |
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CY2PD817
320-MHz 1:7 PECL to PECL/CMOS Buffer
Features
• DC to 320-MHz operation
• 50-ps output-output skew
• 30-ps cycle-cycle jitter
• 2.5V power supply
• LVPECL input @ 320-MHz Operation
• One LVPECL output @ 320-MHz Operation
• Four LVCMOS/LVTTL outputs @ 250 MHz/160 MHz
• Two LVCMOS/LVTTL outputs @ 250 MHz/80 MHz
• 45% to 55% output duty cycle
• Output divider control
• Output enable/disable control
• Operating temperature range: 0°C to +85°C
• 24-pin TSSOP
Description
The CY2PD817 is a low-voltage LVPECL-to-LVPECL and
LVCMOS fanout buffer designed for servers, data communi-
cations, and clock management.
The CY2PD817 is ideal for applications requiring mixed differ-
ential and single-ended clock distribution. This device accepts
an LVPECL input reference clock and provides one LVPECL
and six LVCMOS/LVTTL output clocks. The outputs are parti-
tioned into three banks of one, two, and four outputs. The
LVPECL output is a buffered copy of the input clock while the
LVCMOS outputs are divided by 1, 2, and 4. When CLRDIV is
set HIGH, the output dividers are set to 1. In this mode, the
maximum input frequency is limited to 250 MHz.
When OE is set HIGH, the outputs are disabled in a High-Z
state.
Block Diagram
PCLKI
PCLKI
CLRDIV
OE
÷ 4, ÷ 1
÷ 2, ÷ 1
PCLKO
PCLKO
QA[0:1]
QB[0:3]
Pin Configuration
VDD
PCLKI
PCLKI
VSS
VDD
PCLKO
PCLKO
VSS
OE
VDD
VSS
CLRDIV
1
2
3
4
5
6
7
8
9
10
11
12
24 VDD
23 QA0
22 QA1
21 VSS
20 VDD
19 QB0
18 QB1
17 VSS
16 VDD
15 QB2
14 QB3
13 VSS
24 TSSOP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07574 Rev. **
Revised August 28, 2003
1 page  
CY2PD817
OE
Qn
tQ o n
tQ o ff
Figure 5. Output Enable/Disable Time
Ordering Information
Part Number
CY2PD817ZC
CY2PD817ZCT
Package Type
24-pin TSSOP
24-pin TSSOP – Tape and Reel
Package Drawing and Dimensions
Product Flow
Commercial, 0°C to +85°C
24-lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24
All product and company names mentioned in this document are the trademarks of their respective holders.
51-85119-**
Document #: 38-07574 Rev. **
Page 5 of 6
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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| PDF Descargar | [ Datasheet CY2PD817.PDF ] | |
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