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SPT574 PDF даташит

Спецификация SPT574 изготовлена ​​​​«SPT» и имеет функцию, называемую «COMPLETE 12-BIT uP COMPATIBLE A/D CONVERTER».

Детали детали

Номер произв SPT574
Описание COMPLETE 12-BIT uP COMPATIBLE A/D CONVERTER
Производители SPT
логотип SPT логотип 

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SPT574 Даташит, Описание, Даташиты
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FEATURES
• Improved Version of the HADC574Z
• Complete 12-Bit A/D Converter with Sample/Hold,
Reference and Clock
• Low Power Dissipation (100 mW Max)
• 12-Bit Linearity (Over Temp)
• 25 µs Max Conversion Time
• Single +5 V Supply
• Full Bipolar and Unipolar Input Range
SPT574
FAST, COMPLETE 12-BIT µP COMPATIBLE
A/D CONVERTER WITH SAMPLE/HOLD
APPLICATIONS
• Data Acquisition Systems
• 8 or 12-Bit µP Input Functions
• Process Control Systems
• Test and Scientific Instruments
• Personal Computer Interface
GENERAL DESCRIPTION
The SPT574 is a complete, 12-bit successive approximation
A/D converter manufactured in CMOS technology. The de-
vice is an improved version of the HADC574Z. Included on
chip are an internal reference, clock, and a sample-and-hold.
The S/H is an additional feature not available on similar
devices.
The SPT574 features 25 µs (max) conversion time of 10 or
20 V input signals. Also, a three-state output buffer is added
for direct interface to an 8, 12, or 16-bit µP bus.
The SPT574 has standard bipolar and unipolar input ranges
of 10 V and 20 V that are controlled by a bipolar offset pin and
laser trimmed for specified linearity, gain and offset accuracy.
The power supply is +5 V. The device also has an optional
mode control voltage which may be used depending on the
application. With a maximum dissipation of 100 mW at the
specified voltages, power consumption is about five times
lower than that of currently available devices.
The SPT574 is available in 28-lead ceramic sidebrazed DIP,
PDIP and SOIC packages in the commercial temperature
range.
BLOCK DIAGRAM
Output
Nibble A
Nibble B
Three-State Buffers And Control
Nibble C
STS
12-Bit SAR
Clock
+
Comp
-
Control Logic
Ref
12/8 CS Ao R/C CE
Ref Out
12-Bit
Capacitance
DAC
Offset/Gain
Trim
20 V In
10 V In
BIP Off
AGND
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: [email protected]









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SPT574 Даташит, Описание, Даташиты
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C
Supply Voltages
Mode Control Voltage (VEE to DGND) .................... 0 to +7 V
Logic Supply Voltage (VDD to DGND) ...................0 to +7 V
Analog to Digital Ground (AGND to DGND) ................. ±1 V
Input Voltages
Control Input Voltages (to DGND)
(CE, CS, Ao, 12/8, R/C) ......................... -0.5 to VDD +0.5 V
Analog Input Voltage (to AGND)
(REF IN, BIP OFF, 10 VIN) ...................................... ±16.5 V
20 V VIN Input Voltage (to AGND) .............................. ±24 V
Output
Reference Output Voltage .............. Indefinite Short to GND
Momentary Short to VDD
Temperature
Operating Temperature, Ambient .................... 0 to +70 °C
Junction ......................... +165 °C
Lead Temperature, (Soldering 10 Seconds) ........... +300 °C
Storage Temperature .................................... -65 to +150 °C
Note: Operation at any Absolute Maximum Rating is not implied. See Operating Conditions for proper nominal applied
conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
PARAMETER
TEST
CONDITIONS
TEST
LEVEL
DC ELECTRICAL CHARACTERISTICS
Resolution
Linearity Error
Differential Linearity
TA= 0 to +70 °C
No Missing Codes
Unipolar Offset; 10 V, 20 V +25 °C Adjustable to Zero
Bipolar Offset; ±5 V, ±10 V +25 °C Adjustable to Zero
Full Scale Calibration Error1 +25 °C Adjustable to Zero
Full Scale Calibration Error1
Temperature Coefficients
Unipolar Offset
Bipolar Offset
Full Scale Calibration
No Adjustment to Zero
TA = 0 to +70 °C
Using Internal Reference
Power Supply Rejection
+4.75 V<VDD<+5.25 V
Analog Input Ranges
Bipolar
Max Change in Full
Scale Calibration
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
VI
VI
VI
VI
VI
VI
V
V
V
V
VI
VI
VI
VI
VI
VI
VI
SPT574C
MIN TYP MAX
12
±1
12
±2
±10
0.3
0.47
±1.0
±2.0
±12
±0.5
-5 +5
-10 +10
0 +10
0 +20
15 21
60 84
SPT574B
MIN TYP MAX UNITS
12 Bits
±0.5 LSB
12 Bits
±2 LSB
±4 LSB
0.3 % of FS
0.37 % of FS
±1.0 ppm/°C
±2.0 ppm/°C
±12 ppm/°C
±0.5 LSB
-5 +5 Volts
-10 +10 Volts
0 +10 Volts
0 +20 Volts
15 21
60 84
k
k
SPT
2
SPT574
8/1/00









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SPT574 Даташит, Описание, Даташиты
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
PARAMETER
TEST
CONDITIONS
DC ELECTRICAL CHARACTERISTICS
TEST
LEVEL
SPT574C
MIN TYP MAX
SPT574B
MIN TYP MAX UNITS
Power Supplies Operating
Voltage Range
VDD
VEE2
Operating Current
IDD
IEE2
Power Dissipation
Internal Reference
Voltage
Output Current3
VEE = +5 V
IV +4.5
IV
+5.5
VDD
+4.5
+5.5 Volts
VDD Volts
IV
13 20
13 20 mA
IV 167
167 µA
VI
65 100
65 100 mW
VI 2.4 2.5 2.6 2.4 2.5 2.6 Volts
VI 0.5
0.5 mA
DIGITAL CHARACTERISTICS
Logic Inputs
(CE, CS , R/C , Ao, 12/8 )
Logic 0
Logic1
VI -0.5
VI 2.0
+0.8
5.5
-0.5
2.0
+0.8 Volts
5.5 Volts
Current
VI
-5.0 0. 1
5.0 -5.0 0. 1
5.0 µA
Capacitance
Logic Outputs
(DB11-DB0, STS)
Logic 0
Logic 1
Leakage
Capacitance
V
(ISink = 1.6 mA)
(ISOURCE = 500 µA)
(High Z State,
DB11-DB0 Only)
VI
VI
VI
V
5 5 pF
+2.4
-5
+0.4
+2.4
0.1 +5
-5
5
+0.4 Volts
Volts
0.1 +5 µA
5 pF
AC Accuracy
fS=40 kHz, fIN=10 kHz
Spurious Free Dyn. Range
V
78
78 dB
Total Harmonic Distortion
V -77
-77 dB
Signal-to-Noise Ratio
V 72
72 dB
Signal-to-Noise & Distortion
V 71
71 dB
(SINAD)
Intermodulation Distortion fIN=10 kHz;
V
-75
fIN2=11.5 kHz
Note 1: Fixed 50 resistor from REF OUT to REF IN and REF OUT to BIP OFF.
-75 dB
Note 2: VEE is optional and is only used to set the mode for the internal sample/hold. When not using VEE, the pin should be treated
as a no connect. If VEE is connected to 0 to -15 V, aperture delay (tAP) will increase from 20 ns (typ) to 4000 ns (typ).
Note 3: Available for external loads; external load should not change during conversion.
SPT
3
SPT574
8/1/00










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