DataSheet26.com

IDT72V3673 PDF даташит

Спецификация IDT72V3673 изготовлена ​​​​«IDT» и имеет функцию, называемую «(IDT72V36x3) 3.3 VOLT CMOS SyncFIFOTM».

Детали детали

Номер произв IDT72V3673
Описание (IDT72V36x3) 3.3 VOLT CMOS SyncFIFOTM
Производители IDT
логотип IDT логотип 

30 Pages
scroll

No Preview Available !

IDT72V3673 Даташит, Описание, Даташиты
www.DataSheet4U.com
3.3 VOLT CMOS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36
4,096 x 36
8,192 x 36
IDT72V3653
IDT72V3663
IDT72V3673
FEATURES
Memory storage capacity:
IDT72V3653 – 2,048 x 36
IDT72V3663 – 4,096 x 36
IDT72V3673 – 8,192 x 36
Clock frequencies up to 100 MHz (6.5 ns access time)
Clocked FIFO buffering data from Port A to Port B
IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1,024)
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Retransmit Capability
Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of the 5V operating
IDT723653/723663/723673
Pin compatible with the lower density parts, IDT72V3623/
72V3633/72V3643
Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RS1
RS2
PRS
RT
RTM
FIFO1
Mail1,
Mail2,
Reset
Logic
36
FIFO
Retransmit
Logic
A0-A35
Mail 1
Register
36
RAM ARRAY
2,048 x 36
36
4,096 x 36
8,192 x 36
Write
Pointer
Read
Pointer
MBF1
36
B0-B35
FF/IR
AF
Status Flag
Logic
EF/OR
AE
FS2
FS0/SD
FS1/SEN
36
Programmable Flag
Timing
Offset Registers
Mode
13
MBF2
Mail 2
Register
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFOis a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
36
Port-B
Control
Logic
FWFT
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
4662 drw01
NOVEMBER 2003
DSC-4662/2









No Preview Available !

IDT72V3673 Даташит, Описание, Даташиты
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
DESCRIPTION
TheIDT72V3653/72V3663/72V3673arepinand functionallycompatible
versions of the IDT723653/723663/723673, designed to run off a 3.3V supply
forexceptionallylowpowerconsumption. Thesedevicesaremonolithic,high-
speed, low-power, CMOS unidirectional Synchronous (clocked) FIFO memory
which supports clock frequencies up to 100 MHz and has read access times as
fast as 6.5 ns. The 2,048/4,096/8,192 x 36 dual-port SRAM FIFO buffers data
from Port A to Port B. FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit
formats with a choice of Big- or Little-Endian configurations.
These devices are synchronous (clocked) FIFOs, meaning each port
employs a synchronous interface. All data transfers through a port are gated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals. Theclocksfor
PIN CONFIGURATION
INDEX
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
TQFP (PK128-1, order code: PF)
TOP VIEW
2
102 CLKB
101 Vcc
100 Vcc
99 B35
98 B34
97 B33
96 B32
95 RTM
94 GND
93 B31
92 B30
91 B29
90 B28
89 B27
88 B26
87 Vcc
86 B25
85 B24
84 BM
83 GND
82 B23
81 B22
80 B21
79 B20
78 B19
77 B18
76 GND
75 B17
74 B16
73 SIZE
72 Vcc
71 B15
70 B14
69 B13
68 B12
67 GND
66 B11
65 B10
4662 drw02









No Preview Available !

IDT72V3673 Даташит, Описание, Даташиты
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
COMMERCIALTEMPERATURERANGE
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
Communication between each port may bypass the FIFO via two mailbox
registers. Themailboxregisters'widthmatchestheselectedPortBbuswidth.
Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail
has been stored.
TwokindsofresetareavailableontheseFIFOs: ResetandPartialReset.
Resetinitializesthereadandwritepointerstothefirstlocationofthememoryarray
and selects serial flag programming, parallel flag programming, or one of five
possible default flag offset settings, 8, 16, 64, 256 or 1,024.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings.
The FIFO has Retransmit capability, a Retransmit is performed after four
clock cycles of CLKA and CLKB, by taking the Retransmit pin, RT LOW while
the Retransmit Mode pin, RTM is HIGH. When a Retransmit is performed the
read pointer is reset to the first memory location.
These devices have two modes of operation: In theIDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
word written to an empty FIFO appears automatically on the outputs, no read
operation required (Nevertheless, accessing subsequent words does neces-
sitate a formal read request). The state of the BE/FWFT pin during Reset
determines the mode in use.
The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a
combined Full/Input Ready Flag (FF/IR). The EF and FF functions are
selected in the IDT Standard mode. EF indicates whether or not the FIFO
memory is empty. FF shows whether the memory is full or not. The IR and
OR functions are selected in the First Word Fall Through mode. IR indicates
whether or not the FIFO has available memory locations. OR shows whether
the FIFO has data available for reading or not. It marks the presence of valid
data on the outputs.
The FIFO has a programmable Almost-Empty flag (AE) and a program-
mable Almost-Full flag (AF). AE indicates when a selected number of words
remain in the FIFO memory. AF indicates when the FIFO contains more than
a selected number of words.
FF/IR and AF are two-stage synchronized to the port clock that writes data
into its array. EF/OR andAE are two-stage synchronized to the port clock that
reads data from its array. Programmable offsets for AE and AF are loaded
in parallel using Port A or in serial via the SD input. Five default offset settings
are also provided. The AE threshold can be set at 8, 16, 64, 256 or 1,024
locations from the empty boundary and the AF threshold can be set at 8, 16,
64, 256 or 1,024 locations from the full boundary. All these choices are made
using the FS0, FS1 and FS2 inputs during Reset.
Interspersed Parity is available and can be selected during a Master Reset
of the FIFO. If Interspersed Parity is selected then during parallel programming
of the flag offset values, the device will ignore data line A8. If Non-Interspersed
Parity is selected then data line A8 will become a valid bit.
Two or more devices may be used in parallel to create wider data paths.
In First Word Fall Through mode, more than one device may be connected in
series to create greater word depths. The addition of external components is
unnecessary.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (ICC) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the Power Down state.
The IDT72V3653/72V3663/72V3673 are characterized for operation from
0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by
special order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
3










Скачать PDF:

[ IDT72V3673.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
IDT72V36703.3 VOLT HIGH-DENSITY SUPERSYNC II 36-BIT FIFOIntegrated Device Tech
Integrated Device Tech
IDT72V3672(IDT72V3652 - IDT72V3672) 3.3 VOLT CMOS SyncBiFIFOIDT
IDT
IDT72V3673(IDT72V36x3) 3.3 VOLT CMOS SyncFIFOTMIDT
IDT
IDT72V36763.3 VOLT CMOS TRIPLE BUS SyncFIFOTMIntegrated Device Technology
Integrated Device Technology

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск