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LMK03001C PDF даташит

Спецификация LMK03001C изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «(LMK03000 / LMK03001) Precision Clock Conditioner».

Детали детали

Номер произв LMK03001C
Описание (LMK03000 / LMK03001) Precision Clock Conditioner
Производители National Semiconductor
логотип National Semiconductor логотип 

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LMK03001C Даташит, Описание, Даташиты
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ADVANCE INFORMATION
November 2006
LMK03000/LMK03000C/LMK03001/LMK03001C
Precision Clock Conditioner with Integrated VCO
General Description
The LMK03000/LMK03000C/LMK03001/LMK03001C preci-
sion clock conditioners combine the functions of jitter clean-
ing/reconditioning, multiplication, and distribution of a refer-
ence clock. The devices integrate a Voltage Controlled
Oscillator (VCO), a high performance Integer-N Phase
Locked Loop (PLL), a partially integrated loop filter, three
LVDS, and five LVPECL clock output distribution blocks.
The VCO output is optionally accessible on the Fout port. In-
ternally, the VCO output goes through an Input Divider to feed
the various clock distribution blocks.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
Features
Integrated VCO and Integer-N PLL
Two performance grades (12 kHz to 20 MHz)
LMK03000/LMK03001: Less than 800 fs RMS
LMK03000C/LMK03001C: Less than 400 fs RMS
Two VCO frequency plans
LMK03000/LMK03000C: 1185 to 1296 MHz
LMK03001/LMK03001C: 1470 to 1570 MHz
Clock output frequency range of 1 to 785 MHz
3 LVDS and 5 LVPECL clock outputs
Partially integrated loop filter
Dedicated divider and delay blocks on each clock output
Pin compatible family of clocking devices
3.15 to 3.45 V operation
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
Target Applications
Data Converter Clocking
SONET/SDH, DSLAM
Networking
Wireless Infrastructure
Medical
Test and Measurement
Military / Aerospace
Functional Block Diagram
© 2006 National Semiconductor Corporation 202114
20211401
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LMK03001C Даташит, Описание, Даташиты
Connection Diagram
48-Pin LLP Package
20211402
Pin Descriptions
Pin #
Pin Name
I/O
Description
1, 25
GND
- Ground
2
Fout
O Internal VCO Frequency Output
3, 8, 13, 16, 19, 22, 26,
30, 31, 33, 37, 40, 43, 46
Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6,
Vcc7, Vcc8, Vcc9, Vcc10, Vcc11, Vcc12,
Vcc13, Vcc14
-
Power Supply
4
CLKuWire
I MICROWIRE Clock Input
5
DATAuWire
I MICROWIRE Data Input
6
LEuWire
I MICROWIRE Latch Enable Input
7, 34, 35
NC - No Connection to these pins
9, 10
LDObyp1, LDObyp2
- LDO Bypass
11
GOE
I Global Output Enable
12 LD O Lock Detect and Test Output
14, 15
CLKout0, CLKout0*
O LVDS Clock Output 0
17, 18
CLKout1, CLKout1*
O LVDS Clock Output 1
20, 21
CLKout2, CLKout2*
O LVDS Clock Output 2
23, 24
CLKout3, CLKout3*
O LVPECL Clock Output 3
27
SYNC*
I Global Clock Output Synchronization
28, 29
OSCin, OSCin*
I Oscillator Clock Input; Must be AC coupled
32
CPout
O Charge Pump Output
36 Bias I Bias Bypass
38, 39
CLKout4, CLKout4*
O LVPECL Clock Output 4
41, 42
CLKout5, CLKout5*
O LVPECL Clock Output 5
44, 45
CLKout6, CLKout6*
O LVPECL Clock Output 6
47, 48
CLKout7, CLKout7*
O LVPECL Clock Output 7
DAP
DAP
- Die Attach Pad is Ground
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LMK03001C Даташит, Описание, Даташиты
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors
for availability and specifications.
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature Range
Lead Temperature (solder 4 s)
Symbol
VCC
VIN
TSTG
TL
Ratings
-0.3 to 3.6
-0.3 to (VCC + 0.3)
-65 to 150
+260
Units
V
V
°C
°C
Recommended Operating Conditions
Parameter
Ambient Temperature
Power Supply Voltage
Symbol
TA
VCC
Min
-40
3.15
Typ
25
3.3
Max Units
85 °C
3.45 V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only to the test conditions listed.
Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work
stations. The device is rated to a HBM-ESD of >2 kV, a MM-ESD of >200 V, and a CDM-ESD of >1.2 kV.
Electrical Characteristics
(Vcc = 3.3 V, -40 °C TA 85 °C; Differential Inputs/Outputs; except as specified.)
Symbol
ICC
ICCPD
fOSCin
SLEWOSCin
VOSCin
fCOMP
ISRCECPout
ISINKCPout
Parameter
Power Supply Current
Power Down Current
Reference Oscillator Input Frequency
Range
Reference Oscillator Input Slew Rate
Input voltage for OSCin and OSCin*
Phase Detector Frequency
Charge Pump Source Current
Charge Pump Sink Current
Conditions
Current Consumption
Entire device with one LVPECL and
one LVDS output operating at 765 MHz
in bypass mode (CLKoutX_MUX =
Bypass)
Divider Circuitry (CLKoutX_DIV = 4)
Each clock output
Delay Circuitry (CLKoutX_DLY = 2250
ps)
Each clock output
POWERDOWN = 1
Reference Oscillator
(Note 3)
AC coupled; Single ended
PLL
VCPout = Vcc/2, PLL_CP_GAIN = 1x
VCPout = Vcc/2, PLL_CP_GAIN = 4x
VCPout = Vcc/2, PLL_CP_GAIN = 16x
VCPout = Vcc/2, PLL_CP_GAIN = 32x
VCPout = Vcc/2, PLL_CP_GAIN = 1x
VCPout = Vcc/2, PLL_CP_GAIN = 4x
VCPout = Vcc/2, PLL_CP_GAIN = 16x
VCPout = Vcc/2, PLL_CP_GAIN = 32x
Min
1
0.5
0.2
Typ
162
9
10
1
100
400
1600
3200
-100
-400
-1600
-3200
Max
200
1.6
40
Units
mA
mA
MHz
V/ns
Vpp
MHz
µA
μA
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