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DS26528 PDF даташит

Спецификация DS26528 изготовлена ​​​​«Maxim Integrated Products» и имеет функцию, называемую «Octal T1/E1/J1 Transceiver».

Детали детали

Номер произв DS26528
Описание Octal T1/E1/J1 Transceiver
Производители Maxim Integrated Products
логотип Maxim Integrated Products логотип 

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DS26528 Даташит, Описание, Даташиты
www.DataSheet4U.com
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26528 is a single-chip 8-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each port is independently configurable,
supporting both long-haul and short-haul lines.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
T1/E1/J1
NETWORK
DS26528
T1/J1/E1
Transceiver
x8
BACKPLANE
TDM
DS26528
Octal T1/E1/J1 Transceiver
FEATURES
§ Eight Complete T1, E1, or J1 Long-Haul/Short-
Haul Transceivers (LIU plus Framer)
§ Independent T1, E1, or J1 Selections for Each
Transceiver
§ Internal Software-Selectable Transmit- and
Receive-Side Termination for 100W T1 Twisted
Pair, 110W J1 Twisted Pair, 120W E1 Twisted
Pair, and 75W E1 Coaxial Applications
§ Crystal-Less Jitter Attenuators can be Selected
for Transmit or Receive Path. The Jitter
Attenuator meets ETSI CTR 12/13, ITU G.736,
G.742, G.823, and AT&T PUB 62411.
§ External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
operation. This Clock is Internally Adapted for T1
or E1 Usage in the Host Mode.
§ Receive Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
§ Transmit Open and Short Circuit Detection
§ LIU LOS in Accordance with G.775, ETSI
300233, and T1.231
§ Transmit Synchronizer
§ Flexible Signaling Extraction and Insertion Using
Either the System Interface or Microprocessor
Port
§ Alarm Detection and Insertion
§ T1 Framing Formats of D4, SLC-96, and ESF
§ J1 Support
§ E1 G.704 and CRC-4 Multiframe
§ T1 to E1 Conversion
Features continued in Section 2.
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS26528
-40°C to +85°C 256 TE-CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS26528 Даташит, Описание, Даташиты
DS26528 Octal T1/E1/J1 Transceiver
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................8
2. FEATURE HIGHLIGHTS ....................................................................................................9
2.1 GENERAL..................................................................................................................................... 9
2.2 LINE INTERFACE ........................................................................................................................... 9
2.3 CLOCK SYNTHESIZER ................................................................................................................... 9
2.4 JITTER ATTENUATOR .................................................................................................................... 9
2.5 FRAMER/FORMATTER ................................................................................................................... 9
2.6 SYSTEM INTERFACE ................................................................................................................... 10
2.7 HDLC CONTROLLERS ................................................................................................................ 10
2.8 TEST AND DIAGNOSTICS ............................................................................................................. 11
2.9 CONTROL PORT ......................................................................................................................... 11
3. APPLICATIONS ...............................................................................................................11
4. SPECIFICATIONS COMPLIANCE ...................................................................................12
5. ACRONYMS AND GLOSSARY .......................................................................................14
6. MAJOR OPERATING MODES.........................................................................................15
7. BLOCK DIAGRAMS.........................................................................................................15
8. PIN DESCRIPTIONS ........................................................................................................17
8.1 PIN FUNCTIONAL DESCRIPTION ................................................................................................... 17
9. FUNCTIONAL DESCRIPTION .........................................................................................24
9.1 PROCESSOR INTERFACE ............................................................................................................. 24
9.2 CLOCK STRUCTURE.................................................................................................................... 24
9.3 RESETS AND POWER-DOWN MODES ........................................................................................... 26
9.4 INITIALIZATION AND CONFIGURATION ........................................................................................... 27
9.5 GLOBAL RESOURCES.................................................................................................................. 27
9.6 PER-PORT RESOURCES.............................................................................................................. 27
9.7 DEVICE INTERRUPTS .................................................................................................................. 28
9.8 SYSTEM BACKPLANE INTERFACE ................................................................................................. 30
9.8.1 Elastic Stores ....................................................................................................................................... 30
9.8.2 IBO Multiplexer..................................................................................................................................... 33
9.8.3 H.100 (CT-Bus) Compatibility .............................................................................................................. 40
9.8.4 Transmit and Receive Channel Blocking Registers............................................................................. 41
9.8.5 Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 41
9.8.6 Receive Fractional Support (Gapped Clock Mode) ............................................................................. 41
9.9 FRAMERS................................................................................................................................... 42
9.9.1 T1 Framing ........................................................................................................................................... 42
9.9.2 E1 Framing........................................................................................................................................... 45
9.9.3 T1 Transmit Synchronizer .................................................................................................................... 47
9.9.4 Signaling .............................................................................................................................................. 48
9.9.5 T1 Datalink ........................................................................................................................................... 53
9.9.6 E1 Datalink ........................................................................................................................................... 55
9.9.7 Maintenance and Alarms ..................................................................................................................... 56
9.9.8 E1 Automatic Alarm Generation .......................................................................................................... 59
9.9.9 Error Count Registers .......................................................................................................................... 60
9.9.10 DS0 Monitoring Function...................................................................................................................... 62
9.9.11 Transmit Per-Channel Idle Code Insertion........................................................................................... 63
9.9.12 Receive Per-Channel Idle Code Insertion............................................................................................ 63
9.9.13 Per-Channel Loopback ........................................................................................................................ 63
9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 63
9.9.15 T1 Programmable In-Band Loop Code Generator............................................................................... 64
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DS26528 Даташит, Описание, Даташиты
DS26528 Octal T1/E1/J1 Transceiver
9.9.16 Framer Payload Loopbacks ................................................................................................................. 66
9.10 HDLC CONTROLLERS ............................................................................................................. 67
9.10.1 Receive HDLC Controller..................................................................................................................... 67
9.10.2 Transmit HDLC Controller.................................................................................................................... 70
9.10.3 FIFO Information .................................................................................................................................. 70
9.10.4 HDLC Transmit Example ..................................................................................................................... 70
9.11 LINE INTERFACE UNITS (LIU) ................................................................................................... 72
9.11.1 LIU Operation....................................................................................................................................... 75
9.11.2 Transmitter ........................................................................................................................................... 76
9.11.3 Receiver ............................................................................................................................................... 79
9.11.4 Jitter Attenuator.................................................................................................................................... 81
9.11.5 LIU Loopbacks ..................................................................................................................................... 83
9.12 BIT ERROR RATE TEST FUNCTION (BERT) ............................................................................... 86
9.12.1 BERT Repetitive Pattern Set ............................................................................................................... 87
9.12.2 BERT Error Counter............................................................................................................................. 87
10. DEVICE REGISTERS .......................................................................................................88
10.1 REGISTER LISTINGS ................................................................................................................ 88
10.1.1 Global Register List.............................................................................................................................. 90
10.1.2 Framer Register List............................................................................................................................. 90
10.1.3 LIU and BERT Register List ................................................................................................................. 97
10.2 REGISTER BIT MAPS ............................................................................................................... 98
10.2.1 Global Register Bit Map ....................................................................................................................... 98
10.2.2 Framer Register Bit Map ...................................................................................................................... 99
10.2.3 LIU Register Bit Map .......................................................................................................................... 105
10.2.4 BERT Register Bit Map ...................................................................................................................... 106
10.3 GLOBAL REGISTER DEFINITIONS ............................................................................................ 107
10.4 FRAMER REGISTER DEFINITIONS............................................................................................ 121
10.4.1 Receive Register Definitions .............................................................................................................. 121
10.4.2 Transmit Register Definitions ............................................................................................................. 179
10.5 LIU REGISTER DEFINITIONS................................................................................................... 214
10.6 BERT REGISTER DEFINITIONS............................................................................................... 223
11. FUNCTIONAL TIMING ...................................................................................................231
11.1
11.2
11.3
11.4
T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ........................................................................ 231
T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS .................................................................. 236
E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS........................................................................ 241
E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS .................................................................. 243
12. OPERATING PARAMETERS.........................................................................................246
12.1 LINE INTERFACE CHARACTERISTICS ....................................................................................... 247
13. AC TIMING CHARACTERISTICS ..................................................................................248
13.1
13.2
13.3
MICROPROCESSOR BUS AC CHARACTERISTICS...................................................................... 248
JTAG INTERFACE TIMING ...................................................................................................... 257
SYSTEM CLOCK AC CHARACTERISTICS .................................................................................. 258
14. JTAG-BOUNDARY SCAN AND TEST ACCESS PORT................................................259
14.1
14.2
14.3
14.4
14.5
14.6
INSTRUCTION REGISTER ........................................................................................................ 263
JTAG ID CODES................................................................................................................... 264
TEST REGISTERS .................................................................................................................. 264
BOUNDARY SCAN REGISTER.................................................................................................. 264
BYPASS REGISTER ................................................................................................................ 264
IDENTIFICATION REGISTER..................................................................................................... 264
15. DOCUMENT REVISION HISTORY ................................................................................268
16. PACKAGE INFORMATION............................................................................................269
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