DataSheet26.com

ZL50110 PDF даташит

Спецификация ZL50110 изготовлена ​​​​«Zarlink Semiconductor» и имеет функцию, называемую «(ZL50110 / ZL50114) CESoP Processors».

Детали детали

Номер произв ZL50110
Описание (ZL50110 / ZL50114) CESoP Processors
Производители Zarlink Semiconductor
логотип Zarlink Semiconductor логотип 

70 Pages
scroll

No Preview Available !

ZL50110 Даташит, Описание, Даташиты
www.DataSheet4U.com
ZL50110/11/14
128, 256 and 1024 Channel CESoP
Processors
Data Sheet
Features
General
• Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
• On chip timing & synchronization recovery across
a packet network
• Grooming capability for Nx64 Kbps trunking
Circuit Emulation Services
• Complies with ITU-T recommendation Y.1413
• Complies with IETF PWE3 draft standards for
CESoPSN and SAToP
• Complies with CESoP draft IAs for MEF and MFA
• Structured, synchronous CESoP with clock
recovery
• Unstructured, asynchronous CESoP, with integral
per stream clock recovery
TDM Interfaces
• Up to 32 T1/E1, 8 J2, 2 T3/E3 or 1 STS-1 ports
• H.110, H-MVIP, ST-BUS backplanes
• Up to 1024 bi-directional 64 Kbps channels
October 2005
Ordering Information
ZL50110GAG
ZL50111GAG
ZL50114GAG
552 PBGA
552 PBGA
552 PBGA
Trays, Bake & Drypack
Trays, Bake & Drypack
Trays, Bake & Drypack
-40°C to +85°C
• Direct connection to LIUs, framers, backplanes
• Dual reference Stratum 3, 4 and 4E DPLL for
synchronous operation
Network Interfaces
• Up to 3 x 100 Mbps MII Fast Ethernet or Dual
Redundant 1000 Mbps GMII/TBI Ethernet
Interfaces
System Interfaces
• Flexible 32 bit host CPU interface (Motorola
PowerQUICCcompatible)
• On-chip packet memory for self-contained
operation, with buffer depths of over 16 ms
• Up to 8 Mbytes of off-chip packet memory,
supporting buffer depths of over 128 ms
TDM
Interface
(LIU, Framer, Backplane)
Per Port DCO for
Clock Recovery
Multi-Protocol
Packet
Processing
Engine
PW, RTP, UDP,
IPv4, IPv6, MPLS,
ECID, VLAN, User
Defined, Others
Triple
Packet
Interface
MAC
(MII, GMII, TBI)
On Chip Packet Memory
(Jitter Buffer Compensation for 16-128 ms of Packet Delay Variation)
Dual Reference
Stratum 3 DPLL
Host Processor
Interface
External Memory
Interface (optional)
32-bit Motorola compatible
DMA for signaling packets
ZBT-SRAM
(0 - 8 Mbytes)
Figure 1 - ZL50110/11/14 High Level Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.









No Preview Available !

ZL50110 Даташит, Описание, Даташиты
ZL50110/11/14
Data Sheet
Packet Processing Functions
• Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413., IETF
CESoPSN, IETF SAToP and user programmable
• Packet re-sequencing to allow lost packet detection
• Four classes of service with programmable priority mechanisms (WFQ and SP) using egress queues
• Flexible classification of incoming packets at layers 2, 3, 4, and 5
• Supports up to 128 separate CESoP connections across the Packet Switched Network
Applications
• Circuit Emulation Services over Packet Networks
• Leased Line support over packet networks
• Multi-Tenant Unit access concentration
• TDM over Cable
• Fibre To The Premises G/E-PON
• Layer 2 VPN services
• Customer-premise and Provider Edge Routers and Switches
• Packet switched backplane applications
2
Zarlink Semiconductor Inc.









No Preview Available !

ZL50110 Даташит, Описание, Даташиты
ZL50110/11/14
Data Sheet
Description
The ZL50110/11/14 family of CESoP processors are highly functional TDM to Packet bridging devices. The
ZL50110/11/14 provides both structured and unstructured circuit emulation services over packet (CESoP) for up to
32 T1, 32 E1 and 8 J2 streams across a packet network based on MPLS, IP or Ethernet. The ZL50111 also
supports unstructured T3, E3 and STS-1 streams.
The circuit emulation features in the ZL50110/11/14 family comply with the ITU Recommendation Y.1413, as well as
the emerging CESoP standards from the Metro Ethernet Forum (MEF) and MPLS and Frame Relay Alliance (MFA).
The ZL50110/11/14 also complies with the standards currently being developed within the IETF's PWE3 working
group, listed below.
• Structure-Agnostic TDM over Packet (SAToP) - draft-ietf-pwe3-satop
• Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN) - draft-ietf-
pwe3-cesopsn
The ZL50110/11/14 provides up to triple 100 Mbps MII ports or dual redundant 1000 Mbps GMII/TBI ports.
The ZL50110/11/14 incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing
the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance
and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery
schemes are included, allowing the customer to choose the correct scheme for the application. An externally
supplied clock may also be used to drive the TDM interface of the ZL50110/11/14.
The ZL50110/11/14 incur very low latency for the data flow, thereby increasing QoS when carrying voice services
across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of less than
10 ms, does not require expensive processing such as compression and echo cancellation.
The ZL50110/11/14 is capable of assembling user-defined packets of TDM traffic from the TDM interface and
transmitting them out the packet interfaces using a variety of protocols. The ZL50110/11/14 supports a range of
different packet switched networks, including Ethernet VLANs, IP (both versions 4 and 6) and MPLS. The devices
also supports four different classes of service on packet egress, allowing priority treatment of TDM-based traffic.
This can be used to help minimize latency variation in the TDM data.
Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately
queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface.
Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to
maintain timing integrity.
The ZL50110/11/14 family includes sufficient on-chip memory that external memory is not required in most
applications. This reduces system costs and simplifies the design. For applications that do require more memory
(e.g., high stream count or high latency), the device supports up to 8 Mbytes of SSRAM.
A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor.
This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI
that will run on a Windows PC.
3
Zarlink Semiconductor Inc.










Скачать PDF:

[ ZL50110.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
ZL50110(ZL50110 / ZL50114) CESoP ProcessorsZarlink Semiconductor
Zarlink Semiconductor
ZL50111(ZL50110 / ZL50114) CESoP ProcessorsZarlink Semiconductor
Zarlink Semiconductor
ZL50114(ZL50110 / ZL50114) CESoP ProcessorsZarlink Semiconductor
Zarlink Semiconductor
ZL50115(ZL50115 - ZL50115) CESoP ProcessorsZarlink Semiconductor
Zarlink Semiconductor

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск