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ZL50116 PDF даташит

Спецификация ZL50116 изготовлена ​​​​«Zarlink Semiconductor» и имеет функцию, называемую «(ZL50115 - ZL50115) CESoP Processors».

Детали детали

Номер произв ZL50116
Описание (ZL50115 - ZL50115) CESoP Processors
Производители Zarlink Semiconductor
логотип Zarlink Semiconductor логотип 

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ZL50116 Даташит, Описание, Даташиты
www.DataSheet4U.com
ZL50115/16/17/18/19/20
32, 64 and 128 Channel CESoP
Processors
Data Sheet
Features
General
• Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
• On chip timing & synchronization recovery across
a packet network
• On chip dual reference Stratum 3 DPLL
• Grooming capability for Nx64 Kbps trunking
• Fully compatible with Zarlink's ZL50110, ZL50111
and ZL50114 CESoP processors
Circuit Emulation Services
• Complies with ITU-T recommendation Y.1413
• Complies with IETF PWE3 draft standards
CESoPSN and SAToP
• Complies with CESoP Implementation
Agreements from MEF 8 and MFA 8.0.0
• Structured, synchronous CESoP with clock
recovery
• Unstructured, asynchronous CESoP with integral
per-stream clock recovery
Customer Side TDM Interfaces
• Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports
• H.110, H-MVIP, ST-BUS backplane
April 2005
Ordering Information
ZL50115GAG 324 Ball PBGA
ZL50116GAG 324 Ball PBGA
ZL50117GAG 324 Ball PBGA
ZL50118GAG 324 Ball PBGA
ZL50119GAG 324 Ball PBGA
ZL50120GAG 324 Ball PBGA
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
trays, bake & dry pack
-40°C to +85°C
• Up to 128 bi-directional 64 Kbps channels
• Direct connection to LIUs, framers, backplanes
Customer Side Packet Interfaces
• 100 Mbps MII Fast Ethernet (ZL50118/19/20 only)
(may also be used as a second provider side packet
interface)
Provider Side Packet Interfaces
• 100 Mbps MII Fast Ethernet or 1000 Mbps
GMII/TBI Gigabit Ethernet
TDM
Interface
(LIU, Framer, Backplane)
Per Port DCO for
Clock Recovery
Multi-Protocol
Packet
Processing
Engine
PW, RTP, UDP,
IPv4, IPv6, MPLS,
ECID, VLAN, User
Defined, Others
Dual
Packet
Interface
MAC
(MII, GMII, TBI)
On Chip Packet Memory
(Jitter Buffer Compensation for 128 ms of Packet Delay Variation)
Dual Reference
Stratum 3 DPLL
Host Processor
Interface
JTAG
32-bit Motorola compatible
DMA for signaling packets
Figure 1 - ZL50115/16/17/18/19/20 High Level Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.









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ZL50116 Даташит, Описание, Даташиты
ZL50115/16/17/18/19/20
Data Sheet
System Interfaces
• Flexible 32 bit Motorola host interface
• On-chip packet memory with jitter buffer compensation for over 128 ms of packet delay variation
Packet Processing Functions
• Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413, IETF
CESoPSN, IETF SAToP and user programmable
• Packet re-sequencing to allow lost packet detection and re-ordering
• Four classes of service with programmable priority mechanisms (WFQ and SP) using egress queues
• Programmable classification of incoming packets at layers 2 through 5
• Wire speed processing of all packets regardless of classification providing low latency
• Supports up to 128 separate CESoP connections across the Packet Switched Network
Applications
• Circuit Emulation Services over Packet Networks
• Leased Line support over packet networks
• TDM over Cable
• TDM over WiFi (802.11x)
• TDM over WiMAX (802.16)
• Fibre To The Premises G/E-PON
• Layer 2 VPN services
• Customer-premise and Provider Edge Routers and Switches
• Ethernet and IP based IADs
2
Zarlink Semiconductor Inc.









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ZL50116 Даташит, Описание, Даташиты
ZL50115/16/17/18/19/20
1.0 Changes Summary
The following table captures the changes from the January 2005 issue.
Data Sheet
Page
Item
84 Figure 43
84 Figure 44
Change
Clarified data sheet to indicate ZL5011x supports clock
recovery in both synchronous and asynchronous modes
of operation.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to
conform with default MPC8260. Polarity of CPU_DREQ
and CPU_SDACK remains programmable through API.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to
conform with default MPC8260. Polarity of CPU_DREQ
and CPU_SDACK remains programmable through API.
The following table captures the changes from the November 2004 issue.
Page
38
Item
Section 4.6.1
Change
Added 5 kohm pulldown recommendation to GPIO
signals.
3
Zarlink Semiconductor Inc.










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Номер в каталогеОписаниеПроизводители
ZL50110(ZL50110 / ZL50114) CESoP ProcessorsZarlink Semiconductor
Zarlink Semiconductor
ZL50111(ZL50110 / ZL50114) CESoP ProcessorsZarlink Semiconductor
Zarlink Semiconductor
ZL50114(ZL50110 / ZL50114) CESoP ProcessorsZarlink Semiconductor
Zarlink Semiconductor
ZL50115(ZL50115 - ZL50115) CESoP ProcessorsZarlink Semiconductor
Zarlink Semiconductor

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