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DP83231 PDF даташит

Спецификация DP83231 изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «CRD Device».

Детали детали

Номер произв DP83231
Описание CRD Device
Производители National Semiconductor
логотип National Semiconductor логотип 

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DP83231 Даташит, Описание, Даташиты
www.DataSheet4U.com
February 1991
DP83231 CRDTM Device
(FDDI Clock Recovery Device)
General Description
The DP83231 CRD device is a clock recovery device that
has been designed for use in 100 Mbps FDDI (Fiber Distrib-
uted Data Interface) networks The device receives serial
data from a Fiber Optic Receiver in differential ECL NRZI
4B 5B group code format and outputs resynchronized NRZI
received data and a 125 MHz received clock in differential
ECL format for use by the DP83251 55 PLAYERTM device
Features
Y Clock recovery at 100 Mbps data rate
Y Internal 250 MHz VCO
0 1% VCO operating range
Crystal controlled
Y Precision window centering delay line
Y Single a5V supply
Y 28-pin PLCC package
Y BiCMOS processing
FIGURE 1-1 FDDI Chip Set Block Diagram
TL F 10384 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
BSITM BMACTM PLAYERTM CDDTM and CRDTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10384
RRD-B30M105 Printed in U S A









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DP83231 Даташит, Описание, Даташиты
1 0 FDDI CHIP SET OVERVIEW
2 0 FUNCTIONAL DESCRIPTION
3 0 PIN DESCRIPTIONS
4 0 ELECTRICAL CHARACTERISTICS
4 1 Absolute Maximum Ratings
4 2 Recommended Operating Conditions
4 3 DC Electrical Characteristics
4 3 AC Electrical Characteristics
Table of Contents
5 0 DETAILED INFORMATION
5 1 Special External Components
5 2 Layout Recommendations
5 3 Input and Output Schematics
5 4 Debug Procedure
5 5 AC Test Circuits
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DP83231 Даташит, Описание, Даташиты
1 0 FDDI Chip Set Overview
National Semiconductor’s FDDI chip set consists of five
components as shown in Figure 1-1 For more information
about the other devices in the chip set consult the appropri-
ate data sheets and application notes
DP83231 CRDTM Device
Clock Recovery Device
The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream
Features
 PHY Layer loopback test
 Crystal controlled
 Clock locks in less than 85 ms
DP83241 CDDTM Device
Clock Distribution Device
From a 12 5 MHz reference the Clock Distribution Device
synthesizes the 125 MHz 25 MHz and 12 5 MHz clocks
required by the BSI BMAC and PLAYER devices
DP83251 55 PLAYERTM Device
Physical Layer Controller
The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9 5 Stan-
dard
Features
 4B 5B encoders and decoders
 Framing logic
 Elasticity Buffer Repeat Filter and Smoother
 Line state detector generator
 Link error detector
 Configuration switch
 Full duplex operation
 Separate management port that is used to configure and
control operation
In addition the DP83255 contains an additional
PHY Data request and PHY Data indicate port required
for concentrators and dual attach stations
DP83261 BMACTM Device
Media Access Controller
The BMAC device implements the Timed Token Media Ac-
cess Control protocol defined by the ANSI FDDI X3T9 5
MAC Standard
Features
 All of the standard defined ring service options
 Full duplex operation with through parity
 Supports all FDDI Ring Scheduling Classes (Synchro-
nous Asynchronous etc )
 Supports Individual Group Short Long and External
Addressing
 Generates Beacon Claim and Void frames internally
 Extensive ring and station statistics gathering
 Extensions for MAC level bridging
 Separate management port that is used to configure and
control operation
 Multi-frame streaming interface
DP83265 BSITM Device
System Interface
The BSI Device implements an interface between the Na-
tional FDDI BMAC device and a host system
Features
 32-bit wide Address Data path with byte parity
 Programmable transfer burst sizes of 4 or 8 32-bit words
 Interfaces to low-cost DRAMs or directly to system bus
 Provides 2 Output and 3 Input Channels
 Supports Header Info splitting
 Efficient data structures
 Programmable Big or Little Endian alignment
 Full Duplex data path allows transmission to self
 Comfirmation status batching services
 Receive frame filtering services
 Operates from 12 5 MHz to 25 MHz synchronously with
host system
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Номер в каталогеОписаниеПроизводители
DP83231CRD DeviceNational Semiconductor
National Semiconductor

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