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HY5DU56822BT-D4 PDF даташит

Спецификация HY5DU56822BT-D4 изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «(HY5DU56x22BT-D4x) 256M-P DDR SDRAM».

Детали детали

Номер произв HY5DU56822BT-D4
Описание (HY5DU56x22BT-D4x) 256M-P DDR SDRAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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HY5DU56822BT-D4 Даташит, Описание, Даташиты
www.DataSheet4U.com
HY5DU56422BT-D4/D43
HY5DU56822BT-D4/D43
256M-P DDR SDRAM
HY5DU56422BT-D4/D43
HY5DU56822BT-D4/D43
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.4 / Aug. 2003









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HY5DU56822BT-D4 Даташит, Описание, Даташиты
HY5DU56422BT-D4/D43
HY5DU56822BT-D4/D43
Revision History
1. Revision 0.2 (Jan. 2003)
1) Changed VDDmin from 2.4V to 2.5V at Page22
2) Corrected some typos.
2. Revision 0.3 (Feb. 2003)
1) IDD value update at Page 23, 24.
2) Changed some AC Paramters on AC Characteristics Table at Page27, 28.
3. Revision 0.4 (Aug. 2003)
1) Corrected some contents of Power-Up Sequence and Device Initialization.(tXSNR,tXSRD)
Rev. 0.4 / Aug. 2003
2









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HY5DU56822BT-D4 Даташит, Описание, Даташиты
DESCRIPTION
HY5DU56422BT-D4/D43
HY5DU56822BT-D4/D43
PRELIMINARY
The Hynix HY5DU56422BT ,HY5DU56822BT are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM,
ideally suited for the main memory applications which requires large memory density and high bandwidth.
The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• VDD/VDDQ = 2.5 ~ 2.7V
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• On chip DLL align DQ and DQS transition with CK
transition
• DM mask write data-in at the both rising and falling
edges of the data strobe
ORDERING INFORMATION
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
• CAS latency 3 supported
• Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
• Internal four bank operations with single pulsed
/RAS
• tRAS Lock-out function supported
• Auto refresh and Self refresh supported
• 8192 refresh cycles / 64ms
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
• Full and Half strength driver option controlled by
EMRS
OPERATING FREQUENCY
Part No.
HY5DU56822BT-D*
HY5DU56822BT-D*
Configuration
64Mx4
32Mx8
Package
400mil
66pin
TSOP-II
Grade
- D4
- D43
CL3
200MHz
200MHz
Remark
(CL-tRCD-tRP)
DDR400 (3-4-4)
DDR400 (3-3-3)
* Note : D of speed indicates DDR400.
Rev. 0.4 / Aug. 2003
3










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Номер в каталогеОписаниеПроизводители
HY5DU56822BT-D4(HY5DU56x22BT-D4x) 256M-P DDR SDRAMHynix Semiconductor
Hynix Semiconductor
HY5DU56822BT-D43(HY5DU56x22BT-D4x) 256M-P DDR SDRAMHynix Semiconductor
Hynix Semiconductor

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