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ISL24006 PDF даташит

Спецификация ISL24006 изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «14-Channel Programmable Switchable I2C TFT-LCD Reference Voltage Generator».

Детали детали

Номер произв ISL24006
Описание 14-Channel Programmable Switchable I2C TFT-LCD Reference Voltage Generator
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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ISL24006 Даташит, Описание, Даташиты
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®
Data Sheet
14-Channel Programmable Switchable I2C
TFT-LCD Reference Voltage Generator
with Integrated 4-Channel Static Gamma
Drivers
The ISL24006 is a 14-channel programmable switchable
reference voltage generator with four channels of static
gamma drivers integrated, for a complete 18-channel total
gamma solution for TFT-LCD displays. The 14-channel
programmable switchable configuration allows switching
between two gamma curves.
The ISL24006 is divided into two banks of seven generators:
one designed to cover the range from VREFL_L to VREFL_H;
the remaining seven channels covering the range from
VREFU_L to VREFU_H. Each bank has its own separate high
and low reference inputs, with integrated buffers (four static
gamma drivers) to drive the column driver internal DAC
resistor string to within 0.2V from the top and bottom rails.
An output MUX is used to switch between the two curves in
less than 1µs. Switching is controlled using an external
select pin.
ISL24006 includes an I2C interface for programming the
offset values.
ISL24006 is available in the 38-pin QFN package and is
specified for operation over the -40°C to +85°C temperature
range.
Ordering Information
PART
NUMBER
PACKAGE
TAPE &
REEL
PKG. DWG. #
ISL24006IR-T7
38-Pin QFN
7”
MDP0046
ISL24006IR-T13 38-Pin QFN
13”
MDP0046
ISL24006IRZ
(See Note)
38-Pin QFN
(Pb-Free)
-
MDP0046
ISL24006IRZ-T7
(See Note)
38-Pin QFN
(Pb-Free)
7”
MDP0046
ISL24006IRZ-T13 38-Pin QFN
(See Note)
(Pb-Free)
13”
MDP0046
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
September 9, 2005
ISL24006
FN6110.1
Features
• 14-channel programmable switchable
• 4-channel static
• Fast switch time (< 1µs)
• Programmable with 20mV resolution
• Digital supply 3.3V to 5V
• Supply current of 32mA (without load)
• Rail-to-Rail capability
• I2C interface
• Pb-free plus anneal available (RoHS compliant)
Applications
• TFT-LCD drive circuits
• Reference voltage generators
Pinout
ISL24006
(38-PIN QFN)
TOP VIEW
OUT_REFU_H 1
AVDD 2
STD_REG 3
A0 4
SDA 5
SCL 6
OSC 7
DVDD 8
BANK_SEL 9
NC 10
GND 11
OUT_REFL_L 12
THERMAL
PAD
31 OUT_REFU_L
30 GND
29 BG
28 GND
27 VREFL_L
26 VREFL_H
25 NC
24 NC
23 VREFU_L
22 VREFU_H
21 AVDD
20 OUT_REFL_H
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.









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ISL24006 Даташит, Описание, Даташиты
ISL24006
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage between AVDD and GND . . . . . . . . . . . . . . . . .+18V
Supply Voltage between DVDD and GND lesser of VS or +7V (max)
Maximum Continuous Output Current . . . . . . . . . . . . 20mA/channel
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. The device outputs cannot withstand short-
circuit condition for extended periods of time. To avoid damage, do not exceed absolute maximum rating of 20mA/channel.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications AVDD = 15V, DVDD = 5V, VREFU_H = 14V, VREFU_L = 8.5V, VREFL_H = 6.5V, VREFL_L = 1V, RL = 1kand
CL = 10pF to 1/2 AVDD, TA = 25°C, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN TYP MAX UNIT
SUPPLY
IAVDD
IDVDD
ANALOG
Supply Current
Digital Supply Current
No load
30 38
2.75 4
mA
mA
VOH
VOL
VOH
VOL
PSRR
VAC
IB
REG
BG
OUT1 to OUT7
OUT1 to OUT7
OUT8 to OUT14
OUT8 to OUT14
Power Supply Rejection Ratio
Accuracy
Input Bias Current,
VREF(U_H, U_L, L_H, L_L)
Load Regulation
Band Gap
VREFU_H = 14V, AVDD = 15V
VREFU_L = 8.5V, AVDD = 15V
VREFL_H = 6.5V, AVDD = 15V
VREFL_L = 1.0V, AVDD = 15V
AVDD is moved from 14V to 16V
VREF = 1/2 AVDD
IOUT = 5mA step
13.94
8.47
6.44
0.96
42
-50
13.98
8.51
6.48
1.00
50
0
2
14.02
8.55
6.52
1.04
+50
50
V
V
V
V
dB
mV
nA
0.5 mV/mA
1.1 1.3 1.4
V
SR Slew Rate
8 15
V/µs
tS
DIGITAL
Settling Time
±1/2 LSB
1 µs
VIH Logic 1 Input Voltage
DVDD-
20%
V
VIL
FCLK
RSDIN
tS
tH
Logic 0 Input Voltage
Clock Frequency
SDIN Input Resistance
Setup Time
Hold Time
SCL, SDA, STD_REG
20%*
DVDD
400
V
kHz
1 G
40 ns
40 ns
2 FN6110.1
September 9, 2005









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ISL24006 Даташит, Описание, Даташиты
Block Diagram
ISL24006
VREFU_L
VREFU_H
OSC
INT/EXT
OSCILLATOR
0
C3 DELAY 1
C0
C1
C2
MUX
SCL
SDA
STD_REG
A0
I2C
INTERFACE
AVDD
DVDD
BG
ANALOG
POWER
DIGITAL
POWER
REFERENCE
GENERATOR
MUX
B
BANKA
HI
B
BANKA
LO
DAC HI
DAC LO
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
S/H MUX
S/H
OUT REFU_H
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT REFU_L
OUT REFL_H
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT REFL_L
VREFL_H
VREFL_L
BANK_SEL
3 FN6110.1
September 9, 2005










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