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PDF HY29F400A Data sheet ( Hoja de datos )
| Número de pieza | HY29F400A | |
| Descripción | 4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY29F400A
4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory
KEY FEATURES
5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
High Performance
– Access times as fast as 50 ns
Low Power Consumption
– 20 mA typical active read current in byte
mode, 28 mA typical in word mode
– 30 mA typical program/erase current
– 5 µA maximum CMOS standby current
Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
Sector Erase Architecture
– Boot sector architecture with top and
bottom boot block options available
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and seven 64 Kbyte sectors in byte mode
– One 8 Kword, two 4 Kword, one 16 Kword
and seven 32 Kword sectors in word mode
– A command can erase any combination of
sectors
– Supports full chip erase
Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F400A is a 4 Megabit, 5 volt only CMOS
Flash memory organized as 524,288 (512K) bytes
or 262,144 (256K) words. The device is offered in
industry-standard 44-pin PSOP and 48-pin TSOP
packages.
The HY29F400A can be programmed and erased
in-system with a single 5-volt VCC supply. Internally
generated and regulated voltages are provided for
program and erase operations, so that the device
does not require a high voltage power supply to
perform those functions. The device can also be
programmed in standard EPROM programmers.
Access times as fast as 55 ns over the full operat-
ing voltage range of 5.0 volts ± 10% are offered
for timing compatibility with the zero wait state re-
quirements of high speed microprocessors. A 55
ns version operating over 5.0 volts ± 5% is also
Preliminary
Revision 1.0, January 2002
Sector Protection
– Any combination of sectors may be locked
to prevent program or erase operations
within those sectors
Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 11 sec typical
Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
Ready/Busy# Output (RY/BY#)
– Provides hardware confirmation of
completion of program and erase
operations
100,000 Program/Erase Cycles Minimum
Space Efficient Packaging
– Available in industry-standard 44-pin
PSOP and 48-pin TSOP and reverse
TSOP packages
LOGIC DIAGRAM
18
A[17:0]
CE#
OE#
WE#
RESET#
BYTE#
DQ[7:0]
DQ[14:8]
DQ[15]/A-1
RY/BY#
8
7
1 page  
MEMORY ARRAY ORGANIZATION
The 4 Mbit Flash memory array is organized into
11 blocks called sectors (S0, S1, . . . , S10). A
sector is the smallest unit that can be erased and
which can be protected to prevent accidental or
unauthorized erasure. See the ‘Bus Operations’
and ‘Command Definitions’ sections of this docu-
ment for additional information on these functions.
In the HY29F400A, four of the sectors, which com-
prise the boot block, vary in size from 8 to 32
Kbytes (4 to 16 Kwords), while the remaining
seven sectors are uniformly sized at 64 Kbytes
(32 Kwords). The boot block can be located at
the bottom of the address range (HY29F400AB)
or at the top of the address range (HY29F400AT).
HY29F400A
Table 1 defines the sector addresses and corre-
sponding address ranges for the top and bottom
boot block versions of the HY29F400A.
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
Table 1. HY29F400A Memory Array Organization
Device
Sector
Size
(KB/KW)
Sector Address
A[17] A[16] A[15] A[14] A[13] A[12]
Byte Mode
Address Range 2
S0 64/32 0 0 0 X X X 0x00000 - 0x0FFFF
S1 64/32 0 0 1 X X X 0x10000 - 0x1FFFF
S2 64/32 0 1 0 X X X 0x20000 - 0x2FFFF
S3 64/32 0 1 1 X X X 0x30000 - 0x3FFFF
S4 64/32 1 0 0 X X X 0x40000 - 0x4FFFF
S5 64/32 1 0 1 X X X 0x50000 - 0x5FFFF
S6 64/32 1 1 0 X X X 0x60000 - 0x6FFFF
S7 32/16 1 1 1 0 X X 0x70000 - 0x77FFF
S8 8/4 1 1 1 1 0 0 0x78000 - 0x79FFF
S9 8/4 1 1 1 1 0 1 0x7A000 - 0x7BFFF
S10 16/8 1 1 1 1 1 X 0x7C000 - 0x7FFFF
S0 16/8 0 0 0 0 0 X 0x00000 - 0x03FFF
S1 8/4 0 0 0 0 1 0 0x04000 - 0x05FFF
S2 8/4 0 0 0 0 1 1 0x06000 - 0x07FFF
S3 32/16 0 0 0 1 X X 0x08000 - 0x0FFFF
S4 64/32 0 0 1 X X X 0x10000 - 0x1FFFF
S5 64/32 0 1 0 X X X 0x20000 - 0x2FFFF
S6 64/32 0 1 1 X X X 0x30000 - 0x3FFFF
S7 64/32 1 0 0 X X X 0x40000 - 0x4FFFF
S8 64/32 1 0 1 X X X 0x50000 - 0x5FFFF
S9 64/32 1 1 0 X X X 0x60000 - 0x6FFFF
S10 64/32 1 1 1 X X X 0x70000 - 0x7FFFF
Notes:
1. X indicates Don’t Care.
2. Address in Byte Mode is A[17:-1].
3. Address in Word Mode is A[17:0].
Rev. 1.0/Jan. 02
Word Mode
Address Range 3
0x00000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x17FFF
0x18000 - 0x1FFFF
0x20000 - 0x27FFF
0x28000 - 0x2FFFF
0x30000 - 0x37FFF
0x38000 - 0x3BFFF
0x3C000 - 0x3CFFF
0x3D000 - 0x3DFFF
0x3E000 - 0x3FFFF
0x00000 - 0x01FFF
0x02000 - 0x02FFF
0x03000 - 0x03FFF
0x04000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x17FFF
0x18000 - 0x1FFFF
0x20000 - 0x27FFF
0x28000 - 0x2FFFF
0x30000 - 0x37FFF
0x38000 - 0x3FFFF
5
5 Page 
HY29F400A
Rev. 1.0/Jan. 02
11
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