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PDF ADSP-21363 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-21363 | |
| Descripción | SHARC Processor | |
| Fabricantes | Analog Devices | |
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Preliminary Technical Data
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for professional audio processing
At 333 MHz/2 GFLOPs, with unique audio centric peripherals
such as the Digital Audio Interface the ADSP-21363 SHARC
processor is ideal for applications that require industry
leading equalization, reverberation and other effects
processing
Single-Instruction Multiple-Data (SIMD) computational
architecture
Two 32-bit IEEE floating-point/32-bit fixed-point/40-bit
extended precision floating-point computational units,
each with a multiplier, ALU, shifter, and register file
SHARC® Processor
ADSP-21363
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21363 is available with a 333 MHz core instruction
rate. For complete ordering information, see Ordering
Guide on Page 44
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 X 48-BIT
DAG1
8X4X32
DAG2
8X4X32
PROGRAM
SEQUENCER
BLOCK 0
SRAM
1M BIT ROM
2M BIT
4 BLOCKS OF ON-CHIP MEMORY
BLOCK 1
BLOCK 2
SRAM
1M BIT ROM
2M BIT
SRAM
0.5M BIT
BLOCK 3
SRAM
0.5M BIT
ADDR DATA
ADDR DATA ADDR DATA ADDR DATA
PM ADDRESS BUS
32
DM ADDRESS BUS 32
PM DATA BUS
64
DM DATA BUS 64
IOA IOD
IOA IOD
IOA IOD
IOA IOD
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
PX REGISTER
JTAG TEST & EMULATION
6
S
IOP REGISTERS
(MEMORY MAPPED)
SPI
SPORTS
IDP
PCG
TIMERS
SIGNAL
ROUTING
UNIT
I/O PROCESSOR
AND PERIPHERALS
SEE “ADSP-21363 MEMORY
AND I/O INTERFACE FEATURES”
SECTION FOR DETAILS
Figure 1. Functional Block Diagram – Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781.329.4700
www.analog.com
Fax:781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
ADSP-21363
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21363 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
ADSP-21363 MEMORY AND I/O INTERFACE
FEATURES
The ADSP-21363 adds the following architectural features to
the SIMD SHARC family core.
On-Chip Memory
The ADSP-21363 contains three megabits of internal SRAM
and four megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see Table 2). Each memory block supports single-
cycle, independent accesses by the core processor and I/O pro-
cessor. The ADSP-21363 memory architecture, in combination
with its separate on-chip buses, allow two data transfers from
the core and one from the I/O processor, in a single cycle.
The ADSP-21363’s, SRAM can be configured as a maximum of
96K words of 32-bit data, 192K words of 16-bit data, 64K words
of 48-bit instructions (or 40-bit data), or combinations of differ-
ent word sizes up to three megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-
ing-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Table 2. ADSP-21363 Internal Memory Space
IOP Registers 0x0000 0000 - 0003 FFFF
Long Word (64 bits)
Extended Precision Normal or Normal Word (32 bits)
Instruction Word (48 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 7FFF
BLOCK 0 ROM
0x0008 0000–0x0008 AAAA
BLOCK 0 ROM
0x0008 0000–0x0008 FFFF
Reserved
0x0004 8000–0x0004 BFFF
Reserved
0x0009 0000–0x0009 7FFF
BLOCK 0 RAM
0x0004 C000–0x0004 FFFF
BLOCK 0 RAM
0x0009 0000–0x0009 5555
BLOCK 0 RAM
0x0009 8000–0x0009 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 7FFF
BLOCK 1 ROM
0x000A 0000–0x000A AAAA
BLOCK 1 ROM
0x000A 0000– 0x000A FFFF
Reserved
0x0005 8000–0x0005 BFFF
Reserved
0x000B 0000– 0x000B 7FFF
BLOCK 1 RAM
0x0005 C000–0x0005 FFFF
BLOCK 1 RAM
0x000B 0000–0x000B 5555
BLOCK 1 RAM
0x000B 8000–0x000B FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 1FFF
BLOCK 2 RAM
0x000C 0000–0x000C 2AAA
BLOCK 2 RAM
0x000C 0000–0x000C 3FFF
Reserved
0x0006 2000– 0x0006 FFFF
Reserved
0x000C 4000– 0x000D FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 1FFF
BLOCK 3 RAM
0x000E 0000–0x000E 2AAA
BLOCK 3 RAM
0x000E 0000–0x000E 3FFF
Reserved
0x0007 2000– 0x0007 FFFF
Reserved
0x000E 4000–0x000F FFFF
Short Word (16 bits)
BLOCK 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0012 0000–0x0012 FFFF
BLOCK 0 RAM
0x0013 0000–0x0013 FFFF
BLOCK 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x0016 0000–0x0016 FFFF
BLOCK 1 RAM
0x0017 0000–0x0017 FFFF
BLOCK 2 RAM
0x0018 0000–0x0018 7FFF
Reserved
0x0018 8000–0x001B FFFF
BLOCK 3 RAM
0x001C 0000–0x001C 7FFF
Reserved
0x001C 8000–0x001F FFFF
Reserved
0x0020 0000–0xFFFF FFFF
Rev. PrA | Page 5 of 44 | September 2004
5 Page 
Preliminary Technical Data
ADSP-21363
Table 3. Pin Descriptions (Continued)
Pin
DAI_P20–1
Type
I/O/T
(pu)
State During &
After Reset
Three-state with
programmable
pullup
SPICLK
I/O Three-state with
(pu) pullup enabled
SPIDS
I Input only
MOSI
I/O (O/D) Three-state with
(pu) pullup enabled
MISO
I/O (O/D) Three-state with
(pu) pullup enabled
BOOTCFG1–0 I
Input only
Function
Digital Audio Interface Pins. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the Serial ports, Input data port, precision clock gener-
ators and timers, and SPI to the DAI_P20–1 pins These pins have internal 22.5 kΩ
pullup resistors which are enabled on reset. These pullups can be disabled in the
DAI_PIN_PULLUP register.
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of baud
rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active
during data transfers, only for the length of the transferred word. Slave devices ignore
the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted
out on one clock edge and sampled on the opposite edge of the clock. Clock polarity
and clock phase relative to data are programmable into the SPICTL control register
and define the transfer format. SPICLK has a 22.5 kΩ internal pullup resistor.
Serial Peripheral Interface Slave Device Select. An active low signal used to select
the processor as an SPI slave device. This input signal behaves like a chip select, and
is provided by the master device for the slave devices. In multimaster mode the DSPs
SPIDS signal can be driven by a slave device to signal to the processor (as SPI master)
that an error has occurred, as some other device is also trying to be the master device.
If asserted low when the device is in master mode, it is considered a multimaster error.
For a single-master, multiple-slave configuration where flag pins are used, this pin
must be tied or pulled high to VDDEXT on the master device. For ADSP-21363 to
ADSP-21363 SPI interaction, any of the master ADSP-21363's flag pins can be used to
drive the SPIDS signal on the ADSP-21363 SPI slave device.
SPI Master Out Slave In. If the ADSP-21363 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21363 is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input
data. In an ADSP-21363 SPI interconnection, the data is shifted out from the MOSI
output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a
22.5 kΩ internal pullup resistor.
SPI Master In Slave Out. If the ADSP-21363 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21363 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting
output data. In an ADSP-21363 SPI interconnection, the data is shifted out from the
MISO output pin of the slave and shifted into the MISO input pin of the master. MISO
has a 22.5 kΩ internal pullup resistor. MISO can be configured as O/D by setting the
OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast
transmission to multiple SPI-slaves, the processor's MISO pin may be disabled by
setting (=1) bit 5 (DMISO) of the SPICTL register.
Boot Configuration Select. This pin is used to select the boot mode for the processor.
The BOOTCFG pins must be valid before reset is asserted. See Table 5 for a description
of the boot modes.
Rev. PrA | Page 11 of 44 | September 2004
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADSP-21363.PDF ] | |
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