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PDF CY2PP3220 Data sheet ( Hoja de datos )
| Número de pieza | CY2PP3220 | |
| Descripción | Dual 1:10 Differential Clock / Data Fanout Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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FastEdge™ Series
CY2PP3220
Dual 1:10 Differential Clock/Data Fanout Buffer
Features
• Two sets of ten ECL/PECL differential outputs
• Two ECL/PECL differential inputs
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 150 ps device-to-device skew
• 500 ps propagation delay (typical)
• 1.5 GHz Operation (2.7 GHz max. toggle frequency)
• PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5%
with VEE = 0V
• ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5%
with VCC = 0V
• Industrial temperature range: –40°C to 85°C
• 52-pin 1.4-mm TQFP package
• Temperature compensation like 100K ECL
• Pin compatible with MC100ES6220
Block Diagram
Functional Description
The CY2PP3220 is a low-skew, low propagation delay dual
1-to-10 differential fanout buffer targeted to meet the require-
ments of high-performance clock and data distribution applica-
tions. The device is implemented on SiGe technology and has
a fully differential internal architecture that is optimized to
achieve low signal skews at operating frequencies of up to 1.5
GHz.
The device features two differential input paths that are differ-
ential internally. The CY2PP3220 may function not only as a
differential clock buffer but also as a signal-level translator and
fanout on ECL/PECL signal to twenty ECL/PECL differential
loads. An external bias pin, VBB, is provided for this purpose.
In such an application, the VBB pin should be connected to
either one of the CLKA# or CLKB# inputs and bypassed to
ground via a 0.01-µF capacitor. Traditionally, in ECL, it is used
to provide the reference level to a receiving single-ended input
that might have a different self-bias point.
Since the CY2PP3220 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in com-
munication systems. Furthermore, advanced circuit design
schemes, such as internal temperature compensation, ensure
that the CY2PP3220 delivers consistent performance over
various platforms.
Pin Configuration
VCC
CLKA
CLKA#
VEE
VEE
VCC
CLKB
CLKB#
VEE
VEE
QA0
QA0#
QA9
QA9#
QB0
QB0#
QB9
QB9#
VBB
VCC
VCC
VEE
CLKA
CLKA#
VBB
CLKB
CLKB#
VEE
QB9#
QB9
QB8#
QB8
52
1
51
50 49
48
47 46
45 44
43
42
41 4039
2 38
3 37
4 36
5
6
7 CY2PP3220
35
34
33
8 32
9 31
10 30
11 29
12 28
13 27
14 15 16 17 18 19 20 21 22 23 24 25 26
QA6
QA6#
QA7
QA7#
QA8
QA8#
QA9
QA9#
QB0
QB0#
QB1
QB1#
VCC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07513 Rev.*C
Revised July 28, 2004
1 page  
FastEdge™ Series
CY2PP3220
tr, tf,
20-80%
Figure 2. ECL/LVPECL Output
VO
In p u t
C lo c k
TPLH,
TPD
O u tp u t
C lo c k
A n o th e r
O u tp u t
C lo c k
TPHL
VPP
VO
tS K (O )
Figure 3. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O))
for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
Test Configuration
Standard test load using a differential pulse generator and
differential measurement instrument.
VTT
P ulse
G enerator
Z = 50 ohm
RT = 50 ohm
Zo = 50 ohm
RT = 50 ohm
DUT
CY2PP3220
5"
Zo = 50 ohm
5"
VTT
Figure 4. CY2PP3220 AC Test Reference
VTT
RT = 50 ohm
RT = 50 ohm
VTT
Document #: 38-07513 Rev.*C
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY2PP3220.PDF ] | |
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