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PDF AD7634 Data sheet ( Hoja de datos )
| Número de pieza | AD7634 | |
| Descripción | (AD7631 / AD7634) 18-Bit 250/670 kSPS PulSAR Bipolar Programmable Inputs ADC | |
| Fabricantes | Analog Devices | |
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Preliminary Technical Data
18-Bit 250/670 kSPS PulSAR®
Bipolar Programmable Inputs ADC
AD7631/AD7634
FEATURES
Multiple pins/software programmable input ranges:
±10V, ±5V, 10V, 5V
iCMOS™ process technology
Pins or serial SPI input ranges/mode selection
Throughput:
670kSPS (AD7634)
250kSPS (AD7631)
INL: ± 1.75 LSB (7± ppm of full scale)
DNL: +2/-1 LSB
18-bit resolution with no missing codes
Dynamic range: 102.5 dB typical
SNR: 101 dB typical
THD: -122 dB typical
5V internal reference: typical drift 7ppm/°C; TEMP output
No pipeline delay (SAR architecture)
Parallel (18, 16- or 8-bit bus) and serial 5 V/3.3 V interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation:
190 mW @ 670kSPS
75 mW @ 250kSPS
Pb-free 48-lead LQFP and LFCSP (7x7mm) packages
Pin compatible with other PulSAR ADCs
APPLICATIONS
Process control
High speed data acquisition
Digital signal processing
Spectrum analysis
Instrumentation
Communications
GENERAL DESCRIPTION
The AD7631/AD7634 is an18-bit, charge redistribution
successive approximation register (SAR) architecture analog-to-
digital converter (ADC) with programmable input ranges and
mode selection via a dedicated write only serial interface (or by
hardware pin-strapping). The device is fabricated on ADI’s
patented iCMOS high voltage process. The device contains a
high speed 18-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), and both serial and parallel
system interface ports. Power consumption is automatically
scaled with throughput (AD7634 in Impulse mode), making it
ideal for battery-powered applications. It is available in Pb-free,
48-lead packages with operation specified from −40°C to
+85°C.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND VCC VEE
DVDD DGND
AGND
AVDD
IN+
IN-
REF
REF AMP
SWITCHED
CAP DAC
PDREF
PDBUF
PD
RESET
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
AD7631/
AD7634
SERIAL
PROGRAMMABLE
PORT
SERIAL DATA
PORT
18
PARALLEL
INTERFACE
OVDD
OGND
SPPEN
SPPCLK
SPPDATA
HW/SW
D[17:0]
BUSY
RD
CS
D0/OB/2C
CNVST WARP IMPULSE
MODE0 MODE1
Figure 1.
Table 1. PulSAR® Selection
Type/kSPS
100 to
250
Pseudo
Differential
AD7651,
AD7660
AD7661
True Bipolar
True
Differential
AD7610,
AD7663
AD7675
500 to
570
AD7650
AD7652
AD7664
AD7666
AD7665
AD7676
18-Bit
Multichannel/
Simultaneous
AD7631
AD7678
AD7679
AD7654
AD7655
650 to
1000
AD7653
AD7667
>1000
AD7612,
AD7671
AD7677
AD7634
AD7674
AD7621
AD7622
AD7623
AD7641
AD7643
PRODUCT HIGHLIGHTS
1. Programmable input range and mode selection.
Dedicated write only serial port used for selecting input
range and mode select (mode select AD7634 only).
2. Fast throughput
The AD7634 is 670kSPS and the AD7631 is 250kSPS.
3. Superior Linearity.
No missing 18-bit code. +/- 1.75 LSB typical INL
4. Internal Reference.
5 V internal reference with a typical drift of ±7 ppm/°C
and on-chip TEMP sensor.
5. Serial or Parallel Interface.
Versatile parallel (18, 16- or 8-bit bus) or 2-wire serial
interface arrangement compatible with 3.3 V, or 5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
AD7631/AD7634
Parameter
Operating Current7
AVDD8
DVDD
OVDD
VCC
VEE
VCC
VEE
Power Dissipation
With Internal Reference7
With Internal Reference7
Without Internal Reference
Without Internal Reference7
In Power-Down Mode9
TEMPERATURE RANGE10
Specified Performance
Conditions
PDREF = PDBUF = low
AD7631 @ 250kSPS throughput
AD7634 @ 670kSPS throughput
AD7631 @ 250kSPS throughput
AD7634 @ 670kSPS throughput
AD7631 @ 250kSPS throughput
AD7634 @ 670kSPS throughput
AD7631 @ 250kSPS throughput
AD7631 @ 250kSPS throughput
AD7634 @ 670kSPS throughput
AD7634 @ 670kSPS throughput
AD7631 @ 250kSPS throughput
AD7634 @ 670kSPS throughput
AD7631 @ 250kSPS throughput
AD7634 @ 670kSPS throughput
PD = high
TMIN to TMAX
Min
−40
Typ Max
8.5
21
3.5
7
0.1
0.2
1
0.6
2.8
2
75
190
62
160
2
+85
1 The inputs are differential anti-phase. Refer to the Error! Reference source not found. section.
2 Linearity is tested using endnotes, not best fit.
3 LSB means least significant bit. With the 0 to 5V input range, 1 LSB 38.15μV.
4 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5 Parallel or serial 18-bit.
6 Conversion results are available immediately after completed conversion.
7 Tested in parallel reading mode.
8 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.
9 With all digital inputs forced to OVDD.
10Consult sales for extended temperature range.
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
μW
°C
Rev. PrC | Page 5 of 14
5 Page 
Preliminary Technical Data
AD7631/AD7634
Pin
No. Mnemonic
24 D13
or RDERROR
25 D14
or HW/SW
26 D15
or SPPDATA
27 D16
or SPPCLK
28 D17
or SPPEN
29 BUSY
30 TEN
31 RD
32 CS
33 RESET
34 PD
35 CNVST
36 BIP
37 REF
Type 1
DO
DI/O
DI/O
DI/O
DI/O
DO
DI
DI
Description
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high
while SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low
while SDOUT output is valid.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), read error. In serial slave mode (EXT/INT = high), this output
is used as an incomplete read error flag. If a data read is started and not completed when the
current conversion is complete, the current data is lost and RDERROR is pulsed high.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode) hardware/software select. This input, part of the serial
programmable port, is used to select hardware or software input ranges and mode selection.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial programmable port data. This input is used to write in the
serial programmable port data when HW/SW = low.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial programmable port clock. This input is used to clock in the
data on SPPDATA. The active edge where the data SPPDATA is updated depends on the logic state of
the INVSCLK pin.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial programmable port enable. Asserting this input enables the
serial programmable port.
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.
10 Volt Input Range. Refer to Table 8.
When MODE[1:0] = 0, 1, or 2, this input is used to select the 10V input range.
When MODE[1:0] = 3 (serial mode), and
HW/SW = high, driving TEN high selects the 10 Volt input range.
HW/SW = low, the input range is programmed with the serial programmable port and this pin is a
don’t care.
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
DI Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled.
CS is also used to gate the external clock in slave serial mode.
DI Reset Input. When high, resets the ADC. Current conversion, if any, is aborted. Falling edge of
RESET enables the calibration mode indicated by pulsing BUSY high. If not used, this pin can be tied to
DGND.
DI Power-Down Input. When high, power downs the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion.
DI Bipolar Input Range. Refer to Table 8.
When MODE[1:0] = 0, 1, or 2, this input is used to select the bipolar input range.
When MODE[1:0] = 3 (serial mode), and
HW/SW = high, driving BIP high selects the bipolar input range.
HW/SW = low, the input range is programmed with the serial programmable port and this pin is a
don’t care.
AI/O Reference Output/Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 5 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer.
Rev. PrC | Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AD7634.PDF ] | |
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