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PDF CS4373 Data sheet ( Hoja de datos )
| Número de pieza | CS4373 | |
| Descripción | High-performance Delta-Sigma Test DAC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS4373
Low-power, High-performance ∆Σ Test DAC
Features
• Digital ∆Σ Input, Differential Analog Output
• Selectable Differential Outputs (OUT±, BUF±)
• Selectable Output Attenuation
- 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64
• User-programmable Test Modes
- Differential
- Common mode
• Output Voltage: 5 VP-P Differential
• Outstanding Noise Performance
- 114 dB SNR @ 430 Hz bandwidth
• Low Total Harmonic Distortion
- OUT±: -118 dB THD typical, -112 dB THD max
- BUF±: -100 dB THD typical, -95 dB THD max
• Low Power Consumption
- Normal mode: 7.8 mA
- Low power mode: 5.0 mA
- Power down: 400 µA
- Sleep mode: 2 µA
• Power Supply Options
- VA+ = +5 V; VA- = 0 V; VD = +3.3 V to +5 V
- VA+ = +2.5 V; VA- = -2.5 V; VD = +3.3 V
Description
The CS4373 is a differential output digital-to-
analog converter intended for high-resolution,
low-frequency measurement systems. It is de-
signed to work with the CS5376A and CS5378
digital filters, the CS3301 and CS3302 high-pre-
cision amplifiers, and the CS5371 or CS5372
high-performance ∆Σ modulators.
The CS4373 includes a set of multiplexed out-
puts which provide a precision output (OUT±) for
testing the electronics channel and a buffered
output (BUF±) for in-circuit sensor tests. It is driv-
en by a ∆Σ bitstream and the maximum analog
output is differential 5 volts peak-to-peak. Distor-
tion performance of the DAC is typically -118 dB
THD from the precision output, and -100 dB THD
from the buffered output. Noise performance is
114 dB SNR over a 430 Hz bandwidth.
The CS4373 has very low power consumption. In
normal mode (LPWR=0; MCLK=2.048 MHz),
power consumption is 40 mW; while in Low Pow-
er mode (LPWR=1; MCLK=1.024 MHz), power
consumption is 25 mW.
ORDERING INFORMATION
See page 19.
VA+
MODE(0, 1, 2)
ATT(0, 1, 2)
TDATA
LPW R
MCLK
SYNC
VA-
24-bit ∆Σ
DAC
Attenuator
Clock
Generator
VREF+ VREF-
VD
OUT+
OUT-
BUF+
BUF-
CAP+
CAP-
DGND
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
SEP ‘05
DS577F1
1 page  
CS4373
ANALOG CHARACTERISTICS (CONTINUED)
Parameter
Analog Outputs
Differential Output Level
Absolute Accuracy
Relative Accuracy
Offset Error
Full Scale Drift
Offset Drift
Analog Output Load at BUF±
Voltage Reference Input
VREF
VREF Current
Power Supplies
Power Supply Rejection
DC Power Supply Currents
Symbol
(Note 3)
(Note 3)
Load Resistance
Load Capacitance
VDIF
ABS
REL
VOS
FSD
VOD
RL
CL
(Note 4, 5) VREFV
VREFI
(Note 6) PSRR
(Note 7 and 8)
Min
-
-
-
-
-
-
1
-
-
-
90
Typ
-
±1
±0.2
-
5
1
-
-
2.5
-
-
Max Unit
5
±2
±1.8
1
-
-
-
100
VP-P
%FS
%FS
%FS
ppm/°C
µV/°C
kΩ
pF
-V
120 µA
- dB
Normal Power Mode
LPWR = 0; MCLK = 2.048 MHz
Analog
Digital
VA
VD
- 7.8 - mA
- 100 - µA
Low Power Mode
LPWR = 1; MCLK = 1.024 MHz
Analog
Digital
VA
VD
- 5.0 - mA
- 100 - µA
Power Down Mode
Analog
Digital
VA
VD
- 400 - µA
- 100 - µA
Sleep Mode
Analog
Digital
VA
VD
- 2 - µA
- 2 - µA
3. Specification is for the parameter over the specified temperature range and is for the CS4373 only and
does not include the effects of external components.
4. A 2.5 V voltage reference results in the highest dynamic range and best signal-to-noise performance,
though smaller reference voltages may be used.
5. VREF is defined as {(VREF+) - (VREF-)} and Inputs must satisfy: VA- < VREF- < VREF+ < VA+
6. Power Supply Rejection is tested by applying a 100 mVP-P 50 Hz signal to each supply.
7. All outputs unloaded. All digital inputs forced to VD or GND respectively. VA+ = 5 V; VA- = 0;
VD+ = 3.3 V.
8. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the
signal bandwidth by a factor of 2.
DS577F1
5
5 Page 
CS4373
5.3 Clock Sync Input - SYNC
To synchronize the timing of the digital input
bitstream, the CS4373 uses a SYNC signal.
When using the CS5376A/78 digital filters,
SYNC is automatically generated from a
SYNC signal input from the external system.
The CS4373 SYNC input is rising edge trig-
gered and resets the internal MCLK counter-
divider.
6. VOLTAGE REFERENCE
6.1 Voltage Reference Inputs
The CS4373 is designed to operate with a
2.5 V voltage reference applied across the
VREF+ and VREF- pins.
In a single supply power configuration the
VREF+ pin should be connected to the voltage
reference output, and the VREF- pin connect-
ed to ground. In a dual supply power configu-
ration the voltage reference should be
powered from the VA+ and VA- supplies, with
the VREF+ pin connected to the voltage refer-
ence output and the VREF- pin connected to
VA-. Because most 2.5 V voltage references
require a power supply voltage greater than
3 V to operate, when powering the voltage ref-
erence from dual ±2.5 V supplies the refer-
ence voltage into the VREF+ pin should be
defined relative to the VA- supply (see
Figure 5).
The selected voltage reference should pro-
duce less than 1 µVrms of noise in the mea-
surement bandwidth on the VREF+ pin. The
digital filter output word rate selection deter-
mines the bandwidth over which voltage refer-
ence noise affects the CS4373 dynamic
range.
6.2 Voltage Reference Configurations
For a 2.5 V reference, the Linear Technology
LT1019-2.5 voltage reference yields low
enough noise if the output is filtered with a low
pass RC filter as shown in Figure 5.
6.3 VREF Input Impedance
The switched-capacitor input architecture of
the VREF+ pin causes the input current re-
quired from the voltage reference to change
any time MCLK is changed. The input imped-
ance of the voltage reference input is calculat-
ed similar to the analog signal input
impedance as [1 / (f * C)] where f is the master
clock frequency, MCLK, and C is the internal
sampling capacitor. A 2.048 MHz MCLK yields
a voltage reference input impedance of ap-
proximately [1 / (2.048 MHz)*(20 pF)], or
about 24 kΩ.
DS577F1
VA+
VA-
0.1 µF
LT1019-2.5
2.5V REF
0.1 µF
10 Ω
0.1 µF
+ 100 µF
To VREF+
To VREF -
Figure 5. 2.5 Voltage Reference Circuit
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CS4373.PDF ] | |
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