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PDF SY89828L Data sheet ( Hoja de datos )
| Número de pieza | SY89828L | |
| Descripción | 3.3V 1GHz DUAL 1:10 PRECISION LVDS FANOUT BUFFER/TRANSLATOR | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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MicreL, Inc.
3.3V 1GHz DUAL 1:10 PRECISION
LVDS FANOUT BUFFER/
Precision Edge®
Precision ESdY8g9e8®28L
SY89828L
TRANSLATOR WITH 2:1 INPUT MUX
FEATURES
s High-performance dual 1:10, 1GHz LVDS fanout
buffer/translator
s Two banks of 10 differential LVDS outputs
s Guaranteed AC parameters over temperature and
voltage:
• > 1GHz fMAX
• < 50ps within device skew
• < 400ps tr, tf time
s Each bank includes a 2:1 input mux
s 2:1 mux input accepts LVDS and LVPECL
s Low jitter performance
• < 1psRMS cycle-to-cycle jitter
• < 1psPP total jitter
s 3.3V supply voltage
s Output enable function
s LVDS input includes internal 100Ω termination
s Available in a 64-Pin EPAD-TQFP
APPLICATIONS
s Enterprise networking
s High-end servers
s Communications
TYPICAL APPLICATION CIRCUIT
Precision Edge®
DESCRIPTION
The SY89828L is a precision fanout buffer with 20
differential LVDS (Low Voltage Differential Swing) output
pairs. The part is designed for use in low voltage 3.3V
applications that require a large number of outputs to drive
precisely aligned, ultra low-skew signals to their destination.
The input is multiplexed from either LVDS or LVPECL (Low
Voltage Positive Emitter Coupled Logic) by the CLK_SEL1
and CLK_SEL2 pins. The Output Enables (OE1 and OE2)
are synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.
The SY89828L features a low pin-to-pin skew of less
than 50ps—performance previously unachievable in a
standard product having such a high number of outputs.
The SY89828L is available in a single space saving package,
enabling a lower overall cost solution.
Primary Clock Source
LVDS_CLKA
/LVDS_CLKA
5 100Ω
5
Primary
Card
Backup Clock Source
LVDS_CLKB
/LVDS_CLKB
5 100Ω
Redundant
5 Card
SEL1
Primary/Backup Clock Select
(Switchover with 2.0ns)
System using SY89828L as a switchover circuit from a Primary Clock to a Redundant backup Clock in a fail-safe application.
LVPECL inputs not shown in this application.
Precision Edge is a registered trademark of Micrel, Inc.
M9999-011907
[email protected] or (408) 955-1690
1
Rev.: C Amendment: /0
Issue Date: January 2007
1 page  
MicreL, Inc.
Precision Edge®
SY89828L
TRUTH TABLE
OE1(1) OE2(1) SEL1(1) SEL2(1) CLK_SEL1(1) CLK_SEL2(1)
Q0 – Q9
/Q0 – /Q9
Q10 – Q19
/Q10 – /Q19
11
11
11
11
11
11
11
11
11
11
11
11
01
01
01
01
10
10
10
10
00
0
0
0
0
0
0
1
1
1
1
1
1
X
X
X
X
0
0
1
1
X
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
X
X
X
X
X
0
1
0
0
1
1
0
0
1
1
X
X
0
1
X
X
0
1
X
X
X
X LVDS_CLKA /LVDS_CLKA LVDS_CLKA /LVDS_CLKA
X LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA
0 LVDS_CLKA /LVDS_CLKA LVDS_CLKB /LVDS_CLKB
1 LVDS_CLKA /LVDS_CLKA LVPECL_CLKB /LVPECL_CLKB
0 LVPECL_CLKA /LVPECL_CLKA LVDS_CLKB /LVDS_CLKB
1 LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB
0 LVDS_CLKB /LVDS_CLKB LVDS_CLKA /LVDS_CLKA
1 LVPECL_CLKB /LVPECL_CLKB LVDS_CLKA /LVDS_CLKA
0 LVDS_CLKB /LVDS_CLKB LVPECL_CLKA /LVPECL_CLKA
1 LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA
0 LVDS_CLKB /LVDS_CLKB LVDS_CLKB /LVDS_CLKB
1 LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB
X
LOW
HIGH
LVDS_CLKA /LVDS_CLKA
X
LOW
HIGH
LVPECL_CLKA /LVPECL_CLKA
0
LOW
HIGH
LVDS_CLKB /LVDS_CLKB
1
LOW
HIGH
LVPECL_CLKB /LVPECL_CLKB
X
LVDS_CLKA /LVDS_CLKA
LOW
HIGH
X
LVPECL_CLKA /LVPECL_CLKA
LOW
0
LVDS_CLKB /LVDS_CLKB
LOW
HIGH
HIGH
1
LVPECL_CLKB /LVPECL_CLKB
LOW
HIGH
X
LOW
HIGH
LOW
HIGH
NOTE:
1. Input has internal pull-up so floating input = 1.
M9999-011907
[email protected] or (408) 955-1690
5
5 Page 
MicreL, Inc.
LVPECL/LVDS INPUTS
VCC
Precision Edge®
SY89828L
VCC
1.9k
1.9k
LVPECL_CLK
75k
75k
/LVPECL_CLK
GND
Figure 1. Simplified LVPECL Input Stage
LVDS_CLK
/LVDS_CLK
1.4k
100Ω
1.4k
GND
Figure 2. Simplified LVDS Input Stage
LVDS OUTPUTS
LVDS stands for Low Voltage Differential Swing. LVDS
specifies a small swing of 350mV typical, on a nominal
1.25V common mode above ground. The common mode
voltage has tight limits to permit large variations in ground
between an LVDS driver and receiver. Also, change in
common mode voltage, as a function of data input, is also
kept tight, to keep EMI low.
vOD
vOH, vOL
vOH, vOL
100Ω
50Ω, –1%
50Ω, –1%
vOCM,
˘vOCM
GND
Figure 3. LVDS Differential Measurement
GND
Figure 4. LVDS Common Mode Measurement
QOUT
/QOUT
350mV
(typical)
Figure 5. Output Driver Signal Levels
(Single-Ended)
QOUT
/QOUT
750mV
QOUT — /QOUT
Figure 6. Output Driver Signal Levels
(Differential)
M9999-011907
[email protected] or (408) 955-1690
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SY89828L.PDF ] | |
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