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PDF AN241 Data sheet ( Hoja de datos )
| Número de pieza | AN241 | |
| Descripción | Thermal Considerations | |
| Fabricantes | Philips | |
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Philips Semiconductors Advanced BiCMOS Products
Thermal considerations for advanced logic
families (Futurebus+, ABT and MULTIBYTE)
Application note
AN241
INTRODUCTION
Thermal characteristics of integrated circuit
packages have been and increasingly will be
a major consideration to both producers and
users of electronics products. This is
because an increase in junction temperature
(TJ) can adversely effect the long term
operating life of an IC. The advantages
realized by miniaturization often have
trade–offs in terms of increased junction
temperatures. Some of the variables affecting
TJ are controlled by the IC manufacturer and
others are controlled by the system designer.
Depending on the environment in which the
IC is placed, the user could control well over
75% of the current that flows through the
device.
With the ever increasing use of Surface
Mount Device (SMD) technology,
management of thermal characteristics
becomes a growing concern because not
only are the SMD packages much smaller,
but the thermal energy is concentrated more
densely on the printed wiring board. For
these reasons, designers and manufacturers
of surface mount assemblies must be aware
of all the variables affecting TJ.
POWER DISSIPATION
Power dissipation for the ABT (Advanced
BiCMOS Technology), MULTIBYTE and
Futurebus+ devices can be estimated using
the same equation with the exception of
Futurebus+ transceivers. Due to BTL
OPEN–COLLECTOR outputs, BTL output
swings and the large current driven on the
BTL side (B side) of the transceivers the
equation must be altered.
There are five major factors controlled by the
user which contribute to increased BiCMOS
power dissipation.
1. Frequency of operation (output switching
frequency)
2. Input voltage levels
3. Output loading (capacitive and resistive)
4. VCC level
5. Duty cycle
Each of these five factors are addressed in
the estimating equation except duty cycle.
Duty cycle can be addressed by “weighting”
terms 2, 5, 6, 7 and 8 appropriately.
Conditions under which measurements were
taken and upon which the Power Dissipation
Equation is based are:
1 2 34
s
ƪ ȍ ƫ ƪ ƫPD + VCC CPVCC i+1 FOUTi
) VCC
ICCL
)
2n
ICCH
s
)
ICCL
n
L
)
DICCn3
5 6www.DataSheet4U.com
ƪ ȍ ȍ ƫ) (VCC * VOH)
(VOH
*
VOL)
s
i+1
CLIFOUTiKPi
)
h
i+1
VOH
RDi
78
ƪ ȍ ȍ ƫ) (VOL)
(VOH
*
VOL)
s
i+1
CLIFOUTi
)
l
i+1
(VCC * VOL)
RUi
Power Dissipation Equation
VCC = 5V; 25°C; FOUT = 1, 10, 20, 30, 40,
and 50MHz; 50% duty cycle; CL = 0, 15, 50,
100, and 200pF; also 1, 2, 4, and 8 outputs
switching.
The first current term is due to ICC with the
device unloaded. It is caused by the internal
switching of the device.
ȍs
CPVCC i+1 FOUTi
This term represents the ICC current with
absolutely no load. This measurement was
taken without the output pins connected to
the board. The CP for a device is calculated
by:
CP
+
ICC(@50MHz) * ICC(@1MHz)
VCC(49MHz)s
“s” is the number of outputs switching. CP will
be different for each product type.
The second term is current due to ICC with
the outputs unloaded. This ICC is caused by
switching the bipolar outputs.
(ICCL
)
ICCH)
s
2n
The ICCL and ICCH are the typical values
found in the corresponding product data
sheets. In the case of a 50% duty cycle an
average of ICCL and ICCH will flow through the
device. “n” is the number of outputs on the
device.
The third term is ICCL due to the outputs
being held Low. The ICCH current is in the µA
range so if an output is held or forced High
then there is no appreciable ICC increase.
ICCL
L
n
“L” is the number of outputs held Low.
The fourth term is through current due to
holding the CMOS inputs at 3.4V rather than
at the rail voltages. This term becomes
insignificant as load and frequency increase.
DICCn3
∆ICC is the through current when holding the
input High of a device to 3.4V. This value is
typically 300µA to 500µA. “n3” is the number
of inputs at 3.4V.
The fifth term is current through the upper
structure of the device. It is caused by the
external capacitive load and the output
June, 1992
1
1 page  
Philips Semiconductors Advanced BiCMOS Products
Thermal considerations for advanced logic families
(Futurebus+, ABT and MULTIBYTE)
Application note
AN241
EXAMPLE OF FUTUREBUS+
TRANSCEIVER TJ FOR BTL SIDE
(”A” side can be treated like ABT)
1. Calculate Current Consumption
For example let the FB2031’s CP be 16pF.
Let VCC = 5V; operating temperature = 25°C;
FOUT = 50MHz for 5 outputs switching; hold 2
inputs Low and 2 inputs High (at 3.4V); CL =
100pF; no pull–down; 16.5Ω pull–up.
1
16pF(5V(5)50MHz) = 20mA
+
2
(17mA + 17mA)/2(9) × 5 = 9.44mA
+
3
17mA/9 × 2 + 17mA/9 × 2 = 15.1mA
+
4
.5mA × 2 = 1mA
+
7
1.1V(5)100pF50MHz = 27.5mA
+
8
7(2.1V–1.0V)/16.5Ω = 466.7mA
2. Finding PD (V × I)
The first four current terms are multiplied by
VCC.
5V(20mA + 9.44mA + 15.1mA + 1mA) =
227.7mW
Term seven is multiplied by 1V (VOL).
1V(27.5mA) = 27.5mW
Term eight is also multiplied 1V (VOL).
1V(466.7mA) = 466.7mW
The total estimated power dissipation of an
FB2031 with 5 outputs switching, at 25°C,
with VCC = 5V, with 2 outputs held static Low,
and 2 inputs at 3.4V, with 100pF capacitive
loads, no pull–downs, 16.5Ω pull–ups and
50MHz switching frequency is:
227.7 + 27.5 + 466.7 = 721.9mW
Term eight contributed over 65% of the power
dissipated by the FB2031 in this example.
The power dissipated by the IC with no
external loading totals only 32% of the power.
www.DataSheet4U.com
MODIFYING θJA FOR POWER DISSIPATION AND AIRFLOW
3. Determine θJA
The FB2031 is packaged in the 52–pin
PQFP. Using an average die size of 118 ×
138 yields a θJA of 79°C/W @ 1W power
dissipation (see θJA graph).
4. Determine θJA @ 721.9mW PD
Using the AVERAGE EFFECT of POWER
DISSIPATION on θJA graph calculate the
percentage change in power = (0.7219W –
1W)/1W = –.28 (–28% change) then check
the graph and see that θJA increases by
3.4%. So θJA increases to 79 + 79 × .034 =
81.7°C/W.
5. Assume 200 LFPM Air Flow
Calculate the effects of air flow by referring to
the graph AVERAGE EFFECT of AIR FLOW
on θJA. The θJA is decreased by 22.5%
leaving a θJA of 81.7 – (.225 × 81.7) =
63.3°C/W.
6. Final Calculations for TJ for the FB2031
TJ = (PD × θJA) + Tamb = (0.7219W ×
63.3°C/W) + 70°C = 115.1°C. Referring to the
warnings in the JUNCTION TEMPERATURE
section, a 115.1°C TJ would constitute no
temperature worries.
10
8
6
4
2
%
Change
in θJA
0
–2
–4
–6
–8
TEST POWER
RANGE
.3 TO 3 WATTS
0
–5
–10
–15
% –20
Change
in θJA –25
–30
–35
–40
SO Philips PCB(1.12” × 0.75” × 0.059”)
SOL Philips PCB(1.58” × 0.75” × 0.059”)
PLCC & PQFP Signetics PCB(2.24” ×
2.24” × 0.062””)
DIP Textool ZIF Socket with 0.040”
Stand–off
S
O
SOL
DIP
PLCC,
PQFP
–10
–60 –40 –20
0
20 40 60 80
% Change in Power Dissipation
100 120
Average Effect of Power Dissipation on θJA
–45
0
100 200 300 400 500 600 700 800 900 1000
% Change in Power Dissipation
Average Effect of Air Flow on θJA
June, 1992
5
5 Page 
Philips Semiconductors Advanced BiCMOS Products
Thermal considerations for advanced logic families
(Futurebus+, ABT and MULTIBYTE)
Application note
AN241
TYPICAL THERMAL RESISTANCE (θJC) in °C/W
Typical θJC Data PQFP–52
30
Typical θJC Data PQFP–100
25
25
θJC
PD = 1.0W
20
θJC
PD = 1.0W
20 15
NOTES:
Test Fixture
Accuracy
Infinite Heat Sink
±15%
Data for the 20/24–pin SSOP is preliminary.
Graphs are not yet available. Please see
the table, ”θJA AND θJC CALCULATIONS
FOR ABT, MULTIBYTE, AND
FUTUREBUS+” for the preliminary values.
15
0
5 10 15 20 25 30 35 40
DIE SIZE (SQ MILS × 1000)
10
10 15 20 25 30 35 40 45 50 55 60
DIE SIZE (SQ MILS × 1000)
SYSTEM CONSIDERATIONS
The manner in which an IC package is
mounted and positioned in its surrounding
environment will have significant effects on
operating junction temperatures. These
conditions are under the control of the system
designer and are worthy of serious
consideration in PC board layout and system
ventilation and airflow features.
Forced–air cooling will significantly reduce
θJA. The figure entitled ”AVERAGE EFFECT
OF AIR FLOW ON θJA” provides curves
resulting from Signetics evolution of the effect
of air flow on each of the fundamental
package families. These data are for
approximate linear flow across the long
dimension of the package. Air flow parallel to
the long dimension of the package is
generally a few percent more effective than
air flow perpendicular to the long dimension
of the package. In actual board layouts, other
components can provide air flow blocking and
flow turbulence, which may reflect the net
reduction of θJA of a specific component.
These issues should be carefully evaluated
when using the data presented.
External heat sinks applied to an IC package
can improve thermal resistance by increasing
heat flow to the ambient environment. Heat
sink performance will vary by size, material,
design, and system air flow. Heat sinks can
provide a substantial improvement.
Package mounting can affect thermal
www.DataSheet4U.com
resistance. The data given herein relates to
specific test environments; however, the
general data holds true for other applications.
Surface mount packages dissipate significant
amounts of heat through the leads. Improving
heat flow from package leads to ambient will
decrease thermal resistance. The following
factors have been investigated.
The metal (copper) traces on PC boards
conduct heat away from the package and
dissipate it to the ambient; thus the larger
the trace area the lower the thermal
resistance.
Package stand–off has a small effect on
θJA. Boards with higher thermal conductivity
(ceramic) may show the most pronounced
benefit.
The use of thermally conductive adhesive
under SO packages can lower thermal
resistance by providing a direct heat flow
path from the package to board. Naturally
high thermal conductivity board material
and/or cool board temperatures amplify this
effect.
High thermal conductive board material will
decrease thermal resistance. Data from
Philips indicates that a change in board
material from epoxy laminate to ceramic
reduces thermal resistance.
CONCLUSION
Thermal management remains a major
concern of producers and users of ICs. With
the advent of SMD technology, a thorough
understanding of the thermal characteristics
of both the devices and the systems is very
important. The smaller SMD package does
have a higher θJA than its standard DIP
counterpart — even with copper leadframes.
The increased θJA is the major trade–off one
must accept for package miniaturization.
When the user considers all of the variables
that affect the IC junction temperature, he is
then prepared to take the maximum
advantage of the tools, materials and data
that are available.
June, 1992
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet AN241.PDF ] | |
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