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PDF SI5020 Data sheet ( Hoja de datos )
| Número de pieza | SI5020 | |
| Descripción | SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si5020
SiPHY™ MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC
Features
Complete high speed, low power, CDR solution includes the following:
! Supports OC-48/12/3, STM-16/4/1,
Gigabit Ethernet, and 2.7 Gbps FEC
! Low Power—270 mW (TYP OC-48)
! Small Footprint: 4 mm x 4 mm
! DSPLL™ Eliminates External Loop
Filter Components
! 3.3 V Tolerant Control Inputs
! Exceeds All SONET/SDH
Jitter Specifications
! Jitter Generation
3.0 mUIRMS (TYP)
! Device Power Down
! Loss-of-Lock Indicator
! Single 2.5 V Supply
Applications
! SONET/SDH/ATM Routers
! Add/Drop Multiplexers
! Digital Cross Connects
! Gigabit Ethernet Interfaces
! SONET/SDH Test Equipment
! Optical Transceiver Modules
! SONET/SDH Regenerators
! Board Level Serial Links
Ordering Information:
See page 14.
Pin Assignments
Si5020
Description
www.DataSheet4U.com
The Si5020 is a fully integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1,
or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also
provided for OC-48/STM-16 applications that employ forward error
correction (FEC). DSPLL™ technology eliminates sensitive noise entry
points thus making the PLL less susceptible to board-level interaction and
helping to ensure optimal jitter performance.
The Si5020 represents a new standard in low jitter, low power, and small
size for high speed CDRs. It operates from a single 2.5 V supply over the
industrial temperature range (–40°C to 85°C).
20 19 18 17 16
REXT 1
15 PWRDN/CAL
VDD 2
GND 3
REFCLK+ 4
GND
Pad
14 VDD
13 DOUT+
12 DOUT–
REFCLK– 5
11 VDD
6 7 8 9 10
Top View
Functional Block Diagram
LOL
DIN+
DIN–
2
BUF
Bias
DSPLL™
Phase-Locked
Loop
22
Retimer
BUF
BUF
DOUT+
2 DOUT–
PWRDN/CAL
CLKOUT+
2 CLKOUT–
REXT
RATESEL1–0 REFCLK+
REFCLK–
Preliminary Rev. 0.8 12/00
Copyright © 2000 by Silicon Laboratories
Si5020-DS08
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
1 page  
Si5020
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min1 Typ Max1 Unit
Ambient Temperature
Si5020 Supply Voltage2
TA
VDD
–40
2.375
25
2.5
85
2.625
°C
V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating
conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless
otherwise stated.
2. The Si5020 specifications are guaranteed when using the recommended application circuit (including
component tolerance) of Figure 5 on page 9.
V
SIGNAL+
Differential VICM,VOCM
I/Os SIGNAL–
VIS Single-Ended Voltage
(SIGNAL+) – (SIGNAL–)
Differential
Voltage Swing
VID,VOD (VID = 2VIS)
Differential Peak-to-Peak Voltage
t
Figure 2. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
DOUT
tCf-D
tCr-D
CLKOUT
Figure 3. Clock to Data Timing
DOUT,
CLKOUT
tF
80%
20%
tR
Figure 4. DOUT and CLKOUT Rise/Fall Times
Preliminary Rev. 0.8
5
5 Page 
Si5020
Forward Error Correction (FEC)
The Si5020 supports FEC in SONET OC-48 (SDH
STM-16) applications for data rates up to 2.7 Gbps. In
FEC applications, the appropriate reference clock
frequency is determined by dividing the input data rate
by 16, 32, or 128. For example, if an FEC code is used
that produces a 2.70 Gbps data rate, the required
reference clock would be 168.75 MHz, 84.375 MHz, or
21.09 MHz.
Sinusoidal
Input
Jitter (UI p-p)
15
1.5
0.15
Slope = 20 dB/Decade
Lock Detect
The Si5020 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The circuit compares the frequency of a
divided down version of the recovered clock with the
frequency of the supplied reference clock (REFCLK). If
the recovered clock frequency deviates from that of the
reference clock by the amount specified in Table 4 on
page 8, the PLL is declared out of lock, and the loss-of-
lock (LOL) pin is asserted “high.” In this state, the
DSPLL will periodically try to reacquire lock with the
incoming data stream. During reacquisition, the
recovered clock, CLKOUT, will drift over a ±600 ppm
range relative to the supplied reference clock. The LOL
output will remain asserted until the recovered clock
frequency is within the REFCLK frequency by the
amount specified in Table 4.
Note: LOL is not asserted during PWRDN/CAL.
PLL Performance
The PLL implementation used in the Si5020 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 2, December 1995 and ITU-T G.958.
Jitter Tolerance
The Si5020’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 6. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Note: There are no entries in the mask table for the data rate
corresponding to OC-24 as that rate is not specified by
either GR-253 or G.958.
f0 f1 f2 f3 ft
Frequency
SONET
F0 F1 F2
F3
Ft
Data Rate (Hz) (Hz) (Hz) (kHz) (kHz)
OC-48
10 600 6000 100 1000
OC-12
10 30 300 25
250
OC-3
10 30 300 6.5
65
Figure 6. Jitter Tolerance Specification
Jitter Transfer
The Si5020 is fully compliant with the relevant Bellcore/
ITU specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency (see
Figure 7). These measurements are made with an input
test signal that is degraded with sinusoidal jitter whose
magnitude is defined by the mask in Figure 6.
Jitter Generation
The Si5020 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
Si5020 typically generates less than 3.0 mUI rms of
jitter when presented with jitter-free input data.
Preliminary Rev. 0.8
11
11 Page | ||
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