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Número de pieza | U634H256XS | |
Descripción | PowerStore 32K x 8 nvSRAM Die | |
Fabricantes | Simtek | |
Logotipo | ||
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Obsolete - Not Recommended for New Designs
U634H256XS
PowerStore 32K x 8 nvSRAM Die
Features
Description
• High-performance CMOS non-
volatile static RAM 32768 x 8 bits
• 25, 35 and 45 ns Access Times
• 10, 15 and 20 ns Output Enable
Access Times
• ICC = 15 mA typ. at 200 ns Cycle
Time
• Automatic STORE to EEPROM
on Power Down using external
capacitor
• Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
• Automatic STORE Timing
• 105 STORE cycles to EEPROM
• 10 years data retention in
EEPROM
• Automatic RECALL on Power Up
• Software RECALL Initiation
(RECALL Cycle Time < 20 μs)
• Unlimited RECALL cycles from
EEPROM
• Single 5 V ± 10 % Operation
• Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
• QS 9000 Quality Standard
• ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
The U634H256XS has two sepa-
rate modes of operation: SRAM
mode and nonvolatile mode. In
SRAM mode, the memory operates
as an ordinary static RAM. In non-
volatile operation, data is transfer-
red in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U634H256XS is a fast static
RAM (25, 35, 45 ns), with a nonvo-
latile electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an external
100 μF capacitor.
Transfers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up.
The U634H256XS combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pad
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The chips are tested with a
restricted wafer probe program
at room temperature only. Unte-
sted parameters are marked with
a number sign (#).
Pad Configuration
Pad Description
A5 A6 A7 A12 A14 VCAP VCCX HSB W A13 A8 A9
A4 A11
A3 G
A2
A1
A0
A10
E
DQ0 DQ1 DQ2 VSS VCAPDQ3 DQ4 DQ5 DQ6 DQ7
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
March 31, 2006
STK Control #ML0049
1
Rev 1.0
1 page Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
U634H256XS
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previous Data Valid
tv(A) (9)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
High Impedance
ACTIVE
ten(G) (8)
tPU (10)
STANDBY
tPD (11)
tdis(E) (5)
tdis(G) (6)
Output Data Valid
No.
Switching Characteristics
Write Cycle
Symbol
25 35 45
Unit
Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
tAVAV
tWLWH
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
tAVWL
tAVWH
tELWH
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
tAVAV
tWLEH
tAVEL
tAVEH
tELEH
tDVEH
tEHDX
tEHAX
tcW
tw(W)
tsu(W)
tsu(A)
tsu(A-WH)
tsu(E)
tw(E)
tsu(D)
th(D)
th(A)
tdis(W)
ten(W)
25# 35# 45#
20# 25# 30#
20# 25# 30#
0# 0# 0#
20# 25# 30#
20# 25# 30#
20# 25
30#
10# 12
15#
0# 0# 0#
0# 0# 0#
10# 13# 15#
5# 5# 5#
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
March 31, 2006
STK Control #ML0049
5
Rev 1.0
5 Page Bond pad location and identification table (origin: down left corner)
Pad
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VSS
VCAP
DQ3
DQ4
DQ5
DQ6
DQ7
E
A10
VSE
G
A11
x / μm
135
135
405
960
1170
1445
1653,2
1810,8
2000
2215
2490
2700
2975
3185
3460
3460
3510
3510
3510
y / μm
365
175
140
140
140
140
140
140
140
140
140
140
140
140
175
365
8885
9050
9240
Pad
VSEF
A9
A8
A13
W
HSB
VCCX
VBND
VCAP
VCAP
VBG
A14
A12
A7
A6
A5
A4
A3
U634H256XS
x / μm
3505
3275
3085
2875
2685
2405
2165
1740
1576,8
1419,2
1295
1120
910
720
510
320
85
85
y / μm
9410
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9400
9357,5
9125
The pads VSE, VSEF, VBND, VBG must not be bonded.
Applying any signal or voltage to these pads could damage the chip or influence the functionality.
March 31, 2006
STK Control #ML0049
11
Rev 1.0
11 Page |
Páginas | Total 17 Páginas | |
PDF Descargar | [ Datasheet U634H256XS.PDF ] |
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