PDF CY2SSTU877 Data sheet ( Hoja de datos )

Número de pieza	CY2SSTU877
Descripción	10-Output JEDEC-Compliant Zero Delay Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com PRELIMINARY CY2SSTU877 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer Features • Operating frequency: 125 MHz to 500 MHz • Supports DDRII SDRAM • Ten differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 40 ps • Very low skew: < 40 ps • Power management control input • 1.8V operation • Fully JEDEC-compliant • 52-ball BGA and a 40-pin MLF (QFN) Functional Description The CY2SSTU877 is a high-performance, low-skew, low-jitter zero delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTU877 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTU877 features differential feedback clock outputs and inputs. This allows the CY2SSTU877 to be used as a zero delay buffer. When used as a zero delay buffer in nested clock trees, the CY2SSTU877 locks onto the input reference and translates with near zero delay to low-skew outputs. This phase-locked loop (PLL) clock buffer is designed for a VDD of 1.8V, an AVDD of 1.8V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF (QFN). The device is a zero delay buffer that distributes a differential clock input pair (CK, CK#) to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair feedback clock outputs (FBOUT, FBOUT#). The input clocks (CK, CK#), the feedback clocks (FBIN, FBIN#), the LVCMOS (OE, OS), and the analog power input (AVDD) control the clock outputs. The PLL in the CY2SSTU877 clock driver uses the input clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to provide high-performance, low-skew, low-jitter output differ- ential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CK, CK#) are logic low, the device will enter a low-power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low-power state where all outputs, the feedback, and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FBIN, FBIN#) and the input clock pair (CK, CK#) within the specified stabili- zation time tL. Block Diagram Pin Configuration 52 BGA 12 3 4 A Y1 Y0 Y0# Y5# B Y1# GND GND GND C Y2# GND NB NB D Y2 VDDQ VDDQ VDDQ E CK VDDQ NB NB F CK# VDDQ NB NB G AGND VDDQ VDDQ VDDQ H AVDD GND NB NB J Y3 GND GND GND K Y3# Y4# Y4 Y9 5 Y5 GND GND OS VDDQ OE VDDQ GND GND Y5# 6 Y6 Y6# Y7# Y7 FBIN FBIN# FBOUT# FBOUT Y8 Y8# VDDQ Y2# Y2 CLK CLK# VDDQ AGND AVDD VDDQ GND 40 39 38 1 37 36 35 34 33 32 31 30 2 29 3 28 4 40 QFN 5 CY2SSTU877 27 26 6 25 7 24 8 23 9 22 10 11 12 13 14 15 16 17 18 19 20 21 Y7# Y7 VDDQ FBIN FBIN# FBOUT# FBOUT VDDQ OE OS Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07575 Rev. B Revised January 19, 2005 1 page www.DataSheet4U.com PRELIMINARY CY2SSTU877 Figure 3. Cycle to Cycle Jitter Figure 4. Period Jitter Figure 5. Half Period Jitter Document #: 38-07575 Rev. B Page 5 of 9 5 Page

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