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PDF ASM5I9653A Data sheet ( Hoja de datos )
| Número de pieza | ASM5I9653A | |
| Descripción | 3.3V 1:8 LVCMOS PLL Clock Generator | |
| Fabricantes | Alliance Semiconductor | |
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July 2005
rev 0.2
ASM5I9653A
3.3V 1:8 LVCMOS PLL Clock Generator
Features
1:8 PLL based low-voltage clock generator
Supports zero-delay operation
3.3V power supply
www.DataSheet4U.com Generates clock signals up to 125MHz
PLL guaranteed to lock down to 145MHz, output
frequency = 36.25MHz
Maximum output skew of 150 pS
Differential LVPECL reference clock input
External PLL feedback
Drives up to 16 clock lines
32 lead LQFP & TQFP Packages
Ambient temperature range 0°C to +70°C
Pin and function compatible to the
MPC953,MPC9653A and MPC9653
Functional Description
The ASM5I9653A utilizes PLL technology to frequency lock
its outputs onto an input reference clock. Normal operation
of the ASM5I9653A requires the connection of the QFB
output to the feedback input to close the PLL feedback path
(external feedback). With the PLL locked, the output
frequency is equal to the reference frequency of the device
and VCO_SEL selects the operating frequency range of 25
to 62.5MHz or 50 to 125MHz. The two available post-PLL
dividers selected by VCO_SEL (divide-by-4 or divide-by-8)
and the reference clock frequency determine the VCO
frequency. Both must be selected to match the VCO
frequency range. The internal VCO of the ASM5I9653A is
running at either 4x or 8x of the reference clock frequency.
The ASM5I9653A is guaranteed to lock in a low power PLL
mode in the high frequency range (VCO_SEL = 0) down to
PLL = 145 MHz or Fref = 36.25MHz.
The ASM5I9653A has a differential LVPECL reference
input long with an external feedback input. The device is
ideal for use as a zero delay, low skew fanout buffer. The
device performance has been tuned and optimized for zero
delay performance. The PLL_EN and BYPASS controls
select the PLL bypass configuration for test and diagnosis.
In this configuration, the selected input reference clock is
bypassing the PLL and routed either to the output dividers
or directly to the outputs. The PLL bypass configurations
are fully static and the minimum clock frequency
specification and all other PLL characteristics do not apply.
The outputs can be disabled (high-impedance) and the
device reset by asserting the MR/OE pin. Asserting MR/OE
also causes the PLL to loose lock due to missing feedback
signal presence at FB_IN. Deasserting MR/OE will enable
the outputs and close the phase locked loop, enabling the
PLL to recover to normal operation. The ASM5I9653A is
fully 3.3V compatible and requires no external loop filter
components. The inputs (except PCLK) accept LVCMOS
except signals while the outputs provide LVCMOS
compatible levels with the capability to drive terminated
50Ω transmission lines. For series terminated transmission
lines, each of the ASM5I9653A outputs can drive one or
two traces giving the devices an effective fanout of 1:16.
The device is packaged in a 7x7 mm2 32-lead LQFP &
TQFP Packages.
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
July 2005
ASM5I9653A
rev 0.2
Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)6
Symbol
Characteristics
Min Typ
Input reference frequency
÷4 feedback7
50
fREF
PLL mode, external feedback
÷8 feedback8
25
Max
125
62.5
Unit Condition
MHz PLL locked
MHz PLL locked
fVCO
fVCOlock
fMAX
www.DataSheetV4UP.Pcom
VCMR13
tPW,MIN
Input reference frequency in PLL bypass mode9
VCO operating frequency range10,11
VCO lock frequency range12
Output Frequency
÷4 feedback8
÷8 feedback9
Peak-to-peak input voltage
PCLK
Common Mode Range
Input Reference Pulse Width14
PCLK
0
200
145
50
25
450
1.2
2
200
500
500
125
62.5
1000
VCC-0.75
MHz
MHz
MHz
MHz
MHz
mV
V
nS
PLL locked
PLL locked
LVPECL
LEPVCL
t(Ø) Propagation Delay (static phase offset)15 PCLK to FB_IN -75
125 pS PLL locked
tPD
tsk(O)
tsk(PP)
Propagation Delay
PLL and divider bypass (BYPASS=0), PCLK to Q0-7
PLL disable (BYPASS=1 and PLL_EN=0), PCLK to Q0-7
Output-to-output Skew16
Device-to-device Skew in PLL and divider bypass17
1.2
3.0
3.3 nS
7.0 nS
150 pS
1.5 nS BYPASS=0
DC Output duty cycle
45 50
55 % PLL locked
tR,tF
Output Rise/Fall Time
tPLZ, HZ Output Disable Time
0.1 1.0 nS 0.55 to 2.4V
7.0 nS
tPZL, LZ Output Enable Time
6.0 nS
tJIT(CC) Cycle-to-cycle jitter
100 pS
tJIT(PER)
tJIT(Ø)
BW
tLOCK
Period Jitter
I/O Phase Jitter18
RMS (1 σ)
PLL closed loop bandwidth19
PLL mode, external feedback
Maximum PLL Lock Time
÷ 4 feedback8
÷8 feedback9
100 pS
25 pS
0.8-4
0.5 -1.3
MHz
10 mS
6 AC characteristics apply for parallel output termination of 50Ω to VTT.
7 ÷4 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.
8 ÷8 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.
9 In bypass mode, the ASM3P9653A divides the input reference clock.
10 The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.
11 fVCO is frequency range where AC parameters are guaranteed.
12 fVCOlock is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over fVCO.
13 VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR
range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(Ø ).
14 Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF . 100% and DCREF,MAX = 100% - DCREF,MIN. E.g. at
fREF=100 MHz the input duty cycle range is 20% < DC < 80%.
15 Valid for fREF=50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t(Ø ) [ps] = 50 ps ± (1÷(120 . fREF)).
16 See application section for part-to-part skew calculation in PLL zero-delay mode.
17 For a specified temperature and voltage, includes output skew.
18 I/O phase jitter is reference frequency dependent. See application section for details.
19 -3 dB point of PLL transfer characteristics.
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
5 of 13
5 Page 
July 2005
rev 0.2
www.DataSheet4U.com
32-lead LQFP Package
ASM5I9653A
SECTION A-A
Symbol
A
A1
A2
D
D1
E
E1
L
L1
T
T1
b
b1
R0
e
a
Dimensions
Inches
Millimeters
Min Max Min Max
….
0.0630
…
1.6
0.0020
0.0059
0.05
0.15
0.0531
0.0571
1.35
1.45
0.3465
0.3622
8.8
9.2
0.2717
0.2795
6.9
7.1
0.3465
0.3622
8.8
9.2
0.2717
0.2795
6.9
7.1
0.0177
0.0295
0.45
0.75
0.03937 REF
1.00 REF
0.0035
0.0079
0.09
0.2
0.0038
0.0062
0.097
0.157
0.0118
0.0177
0.30
0.45
0.0118
0.0157
0.30
0.40
0.0031
0.0079
0.08
0.20
0.031 BASE
0.8 BASE
0° 7° 0° 7°
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
11 of 13
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ASM5I9653A.PDF ] | |
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