|
|
PDF ASM5I9775A Data sheet ( Hoja de datos )
| Número de pieza | ASM5I9775A | |
| Descripción | 14-Output Zero Delay Buffer | |
| Fabricantes | Alliance Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ASM5I9775A (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
June 2005
ASM5I9775A
rev 0.3
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
General Features
Output frequency range: 8.3MHz to 200MHz
Input frequency range: 4.2MHz to 125MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
www.DataSheet4U.co1mFeedback clock output
2 LVCMOS reference clock inputs
150 pS max output-output skew
PLL bypass mode
‘SpreadTrak’
Output enable/disable
Industrial temperature range: –40°C to +85°C
52 Pin 1.0 mm TQFP Package
RoHS Compliance
Functional Description
The ASM5I9775A is a low-voltage high-performance
200 MHz PLL-based zero delay buffer designed for high-
speed clock distribution applications. The ASM5I9775A
features two reference clock inputs and provides
14 outputs partitioned in 3 banks of 5, 5, and 4 outputs.
Bank A and Bank B divide the VCO output by 4 or 8 while
Bank C divides by 8 or 12 per SEL(A:C) settings, see
Functional Table. These dividers allow output to input
ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each
LVCMOS compatible output can drive 50Ω series or
parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one
or two traces giving the device an effective fanout of 1:28.
The PLL is ensured stable, given that the VCO is
configured to run between 200 MHz and 500 MHz. This
allows a wide range of output frequencies from 8.3 MHz
to 200 MHz. For normal operation, the external feedback
input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the
input reference clock set by the feedback divider, see
Frequency Table. When PLL_EN is LOW, PLL is
bypassed and the reference clock directly feeds the
output dividers. This mode is fully static and the minimum
input clock frequency specification does not apply.
Block Diagram
VCO_SEL (1, 0)
PLL_EN
TCLK_SEL
TCLK0
TCLK1
FB_IN
SELA
SELB
.
PLL
200-
500MHZ
+2
+4
+2/+4
CLK
STOP
+2/+4
CLK
STOP
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QB4
SELC
CLK_STP#
FB_SEL(1.0)
MR#/OE
+4/+6
CLK
STOP
+4/+6/+8/+12
QC0
QC1
QC2
QC3
FB_OUT
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
June 2005
ASM5I9775A
rev 0.3
Table 3. Function Table (Bank A, B, and C)
VCO_SEL1
0
0
0
0
1
www.DataSheet4U.com 1
VCO_SEL0
0
0
1
1
x
x
SELA
0
1
0
1
0
1
Table 4. Function Table (FB_OUT)
QA(4:0)
÷4
÷8
÷8
÷16
÷2
÷4
SELB
0
1
0
1
0
1
QB(4:0)
÷4
÷8
÷8
÷16
÷2
÷4
SELC
0
1
0
1
0
1
QC(3:0)
÷8
÷12
÷16
÷24
÷4
÷6
VCO_SEL1
0
0
0
0
0
0
0
0
1
1
1
1
VCO_SEL0
0
0
0
0
1
1
1
1
x
x
x
x
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
FB_OUT
÷8
÷16
÷12
÷24
÷16
÷32
÷24
÷48
÷4
÷8
÷6
÷12
Absolute Maximum Conditions
Parameter
VDD
VDD
VIN
VOUT
VTT
LU
RPS
TS
TA
TJ
ØJC
ØJA
ESDH
FIT
Description
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch Up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Condition
Functional
Relative to VSS
Relative to VSS
Functional
Ripple Frequency < 100 kHz
Non Functional
Functional
Functional
Functional
Functional
Manufacturing test
Min
-0.3
2.375
-0.3
-0.3
-
200
-
-65
-40
-
-
-
2000
Max
5.5
3.465
VDD+ 0.3
VDD+ 0.3
VDD ÷2
-
150
+150
+85
150
23
55
-
10
Unit
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
Volts
ppm
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
5 of 12
5 Page 
June 2005
rev 0.3
Ordering Information
Part Number
ASM5I9775A-52-ET
ASM5I9775A-52-ER
ASM5I9775AG-52-ET
ASM5I9775AG-52-ER
Marking
ASM5I9775A
ASM5I9775A
ASM5I9775AG
ASM5I9775AG
Package Type
52-pin TQFP, Tray
52-pin TQFP – Tape and Reel
52-pin TQFP, Tray, Green
52-pin TQFP – Tape and Reel, Green
www.DataSheetD4Ue.vcoicme Ordering Information
ASM5I9775AG-52-ET
ASM5I9775A
Operating Range
Industrial
Industrial
Industrial
Industrial
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
DEVICE PIN COUNT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive I= Industrial P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ASM5I9775A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ASM5I9775A | 14-Output Zero Delay Buffer | Alliance Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |