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Número de pieza | CY29350 | |
Descripción | 9-Output Clock Driver | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
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No Preview Available ! CY29350
2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
Features
• Output frequency range: 25 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 31.25 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2.5% max Output duty cycle variation
www.DataSheet•4UN.cinome Clock outputs: Drive up to 18 clock lines
• Two reference clock inputs: Xtal or LVCMOS
• 150-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9350
• Industrial temperature range: –40°C to +85°C
• 32-pin 1.0mm TQFP package
Block Diagram
Functional Description
The CY29350 is a low-voltage high-performance 200-MHz
PLL-based clock driver designed for high speed clock distri-
bution applications.
The CY29350 features Xtal and LVCMOS reference clock
inputs and provides nine outputs partitioned in four banks of 1,
1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4
while the other banks divide by 4 or 8 per SEL(A:D) settings,
see . These dividers allow output to input ratios of 16:1, 8:1,
4:1, and 2:1. Each LVCMOS compatible output can drive 50Ω
series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 200 MHz. The internal
VCO is running at multiples of the input reference clock set by
the feedback divider, see Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Pin Configuration
SELA
PLL_EN
REF_SEL
TCLK
XIN
XOUT
OSC
FB_SEL
SELB
SELC
Phase
Detector
VCO
200 -
500MHz
LPF
÷16 / ÷32
SELD
÷2 / ÷4
÷4 / ÷8
÷4 / ÷8
÷4 / ÷8
OE#
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
AVDD
FB_SEL
SELA
SELB
SELC
SELD
AVSS
XOUT
1 24 QC0
2 23 VDDQC
3 22 QC1
4
5
CY29350
21
20
VSS
QD0
6 19 VDDQD
7 18 QD1
8 17 VSS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07474 Rev. *A
Revised July 26, 2004
1 page CY29350
AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C)(continued)[6]
Parameter
Description
Condition
Min.
BW
PLL Closed Loop Bandwidth
÷16 Feedback
(–3dB)
÷32 Feedback
–
–
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
Multiple frequencies
–
–
tJIT(PER)
Period Jitter
Same frequency
Multiple frequencies
–
–
tLOCK
Maximum PLL Lock Time
–
Typ.
0.7 – 0.9
0.6 – 0.8
–
–
–
–
–
Max.
–
–
150
250
100
150
1
Unit
MHz
ps
ps
ms
www.DataSheet4U.com
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
RT = 50 ohm
Zo = 50 ohm
RT = 50 ohm
VTT
Figure 1. AC Test Reference for VDD = 3.3V / 2.5V
VDD
VDD/2
tP
GND
T0
VTT
DC = tP / T0 x 100%
Figure 2. Output Duty Cycle (DC)
tSK(O)
VDD
VDD/2
GND
VDD
VDD/2
GND
Figure 3. Output-to-Output Skew , tsk(O)
Table 3. Suggested Oscillator Crystal Parameters
Characteristic
Frequency Tolerance
Frequency Temperature Stability
Aging
Load Capacitance
Effective Series Resistance
Symbol
TC
TS
TA
CL
RESR
Conditions
(TA –10 +60C)
First three years @ 25C
Crystal’s rated load
Ordering Information
Part Number
CY29350AI
CY29350AIT
Package Type
32-pin TQFP
32-pin TQFP – Tape and Reel
Min Typ
Max
– – ±100
– – ±00
––
5
– 20
–
– 40 80
Units
PPM
PPM
PPM/yr
pF
Ω
Product Flow
Industrial, –40°C to +85°C
Industrial, –40°C to 85°C
Document #: 38-07474 Rev. *A
Page 5 of 7
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet CY29350.PDF ] |
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