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PDF AS7C251MNTF32A Data sheet ( Hoja de datos )
| Número de pieza | AS7C251MNTF32A | |
| Descripción | (AS7C251MNTF32A / AS7C251MNTF36A) 2.5V 1M x 32/36 Flowthrough SRAM | |
| Fabricantes | Alliance Semiconductor Corporation | |
| Logotipo |  |
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December 2004
AS7C251MNTF32A
AS7C251MNTF36A
®
2.5V 1M × 32/36 Flowthrough SRAM with NTDTM
Features
• Organization: 1,048,576 words × 32 or 36 bits
• NTD™architecture for efficient bus operation
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
www.DataSheet4U.com
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
A[19:0]
20
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
DQ
Aredgdirsetesrs
Burst logic
CLK
Control
logic
CLK
DQ[a,b,c,d] 32/36
D Data
Input
Q
Register
CLK
20
DQ
Write delay
addr. registers
CLK
20
CLK
32/36
1M x 32/36
SRAM
Array
32/36 32/36
CLK
CEN
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
OE
-75
8.5
7.5
325
140
90
32/36
Output
Buffer
OE
32/36
DQ[a,b,c,d]
-85 -10
10 12
8.5 10
300 275
130 130
90 90
Units
ns
ns
mA
mA
mA
12/23/04, v 1.1
Alliance Semiconductor
P. 1 of 18
Copyright © Alliance Semiconductor. All rights reserved.
1 page  
AS7C251MNTF32A/36A
®
Signal descriptions
Signal I/O Properties
Description
CLK
I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
CEN
I SYNC Clock enable. When de-asserted high, the clock input signal is masked.
A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted.
DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE is active.
CE0, CE1,
CE2
I
SYNC
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
www.DataSheetA4UD.cVom/LD
I
SYNC
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. When low, a new address is loaded.
R/W
I
SYNC
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
BW[a,b,c,d] I
SYNC
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.
LBO
I
STATIC
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
NC - - No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ
become disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successful
complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly,
when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of
SNOOZE MODE.
12/23/04, v 1.1
Alliance Semiconductor
P. 5 of 18
5 Page 
Timing waveform of write cycle
CLK
tCENS tCENH
CEN
www.DataSheet4U.com
Address
tAS tAH
A1
A2
®
tCH tCL
AS7C251MNTF32A/36A
tCYC
A3
R/W
BWn
tCSS tCSH
CE0,CE2
CE1
ADV/LD
tADVS tADVH
OE
Din
Dout
D(A1)
tHZOE
Q(n-1)
D(A2)
D(A2Y‘01) D(A2Y‘10)
tDS tDH
D(A3)
D(A2Y‘11)
D(A3Y‘01)
Command
WRITE DSEL
D(A1)
WRITE
D(A2)
BURST BURST BURST STALL
WRITE WRITE WRITE
D(A2Ý01) D(A2Ý10) D(A2Ý11)
WRITE
D(A3)
BURST
WRITE
D(A3Ý01)
12/23/04, v 1.1
Alliance Semiconductor
P. 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AS7C251MNTF32A.PDF ] | |
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